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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックMCF5235 bdm documentation</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5235-bdm-documentation/m-p/134935#M1532</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am currently working on better patch to support the coldfire 2/2M processors with the m68k-bdm [1]. Working on that project I found the following information in the manuals:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Coldfire 2/2M Users Manual: 7-22, page 159:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Control Register Map for Read Control Register (RCREG) command:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;RAMBAR0 = $C04&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;MCF5235 Manual: 3-8, page 697:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Control Register Map for Read Control Register (RCREG) command:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;RAMBAR = $C05&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From testing I known that the second value is correct but I am still wondering why it was chosen this way. Does that mean that a debugger can't treat all Coldfire 2 cores in the same way? I wanted to make only a distinction between 2 and 2M cores (the later one having the MAC registers).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Christian Walter&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;[1] &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fsourceforge.net%2Fprojects%2Fbdm%2F" rel="nofollow" target="_blank"&gt;http://sourceforge.net/projects/bdm/&lt;/A&gt;&lt;/SPAN&gt;&lt;P&gt;Message Edited by wolti on &lt;SPAN class="date_text"&gt;05-06-2006&lt;/SPAN&gt;&lt;SPAN class="time_text"&gt;04:00 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 07 May 2006 03:59:20 GMT</pubDate>
    <dc:creator>wolti</dc:creator>
    <dc:date>2006-05-07T03:59:20Z</dc:date>
    <item>
      <title>MCF5235 bdm documentation</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5235-bdm-documentation/m-p/134935#M1532</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am currently working on better patch to support the coldfire 2/2M processors with the m68k-bdm [1]. Working on that project I found the following information in the manuals:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Coldfire 2/2M Users Manual: 7-22, page 159:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Control Register Map for Read Control Register (RCREG) command:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;RAMBAR0 = $C04&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;MCF5235 Manual: 3-8, page 697:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Control Register Map for Read Control Register (RCREG) command:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;RAMBAR = $C05&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From testing I known that the second value is correct but I am still wondering why it was chosen this way. Does that mean that a debugger can't treat all Coldfire 2 cores in the same way? I wanted to make only a distinction between 2 and 2M cores (the later one having the MAC registers).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Christian Walter&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;[1] &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fsourceforge.net%2Fprojects%2Fbdm%2F" rel="nofollow" target="_blank"&gt;http://sourceforge.net/projects/bdm/&lt;/A&gt;&lt;/SPAN&gt;&lt;P&gt;Message Edited by wolti on &lt;SPAN class="date_text"&gt;05-06-2006&lt;/SPAN&gt;&lt;SPAN class="time_text"&gt;04:00 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 07 May 2006 03:59:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5235-bdm-documentation/m-p/134935#M1532</guid>
      <dc:creator>wolti</dc:creator>
      <dc:date>2006-05-07T03:59:20Z</dc:date>
    </item>
    <item>
      <title>Re: MCF5235 bdm documentation</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5235-bdm-documentation/m-p/134936#M1533</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;P&gt;Hi Christian,&lt;/P&gt;&lt;P&gt;The ColdFire 2/2M is very old documenation and the MCF5235 documenation is much newer.&lt;/P&gt;&lt;P&gt;The RAMBAR address did change from older to newer versions (it keeps the chip designers busy!).&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards, DavidS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 May 2006 20:30:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/MCF5235-bdm-documentation/m-p/134936#M1533</guid>
      <dc:creator>DavidS</dc:creator>
      <dc:date>2006-05-18T20:30:31Z</dc:date>
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