MCF5271 - memory mapping

Anand — Fri, 25 May 2007 06:57:26 GMT

The MCF5271 reference manual says that it has a 4GB address space but there are only 24 address pins. How do I interface 4GB of memory using 24 address pins. Also can someone explain the functionality of BS[3:0] pins in detail.

Also please send any document or notes which will help me understand.

Any help will be appreciated.

Re: MCF5271 - memory mapping

SimonMarsden_de — Fri, 25 May 2007 15:38:50 GMT

Internally, the MCF5271 has a 32-bit address bus, so in theory it could address 4GB of memory. Not all of the address bus lines are brought out to external pins, so you might think that this limited the memory space.

However, when interfacing to SDRAM memory, the address bus is multiplexed - i.e. the logical address is broken down into two parts called a 'row' address and a 'column' address.

To access a value in SDRAM memory, the SDRAM controller first places the row' address on the address bus, and the SDRAM memory stores this. The SDRAM controller then sends the 'column' address, and the data transfer takes place.

(For subsequent memory accesses with the same row address, the SDRAM controller can just change the column address, making for a faster access).

In practical terms, this means that a logical address is broken down into two parts, so the number of external pins is not a limiting factor.

ColdFire/68K Microcontrollers and Processors中的主题 Re: MCF5271 - memory mapping

MCF5271 - memory mapping

Re: MCF5271 - memory mapping