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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: Regarding IEEE 1588</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-IEEE-1588/m-p/1190580#M14026</link>
    <description>&lt;P&gt;Look at Figure&amp;nbsp; 4 in that document. Note the part that starts "&lt;SPAN&gt;Variable delay introduced &lt;/SPAN&gt;&lt;SPAN&gt;by the Network due to the &lt;/SPAN&gt;&lt;SPAN&gt;topology:". And that the protocol automatically handles this.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;BR /&gt;Tom&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sun, 29 Nov 2020 22:16:46 GMT</pubDate>
    <dc:creator>TomE</dc:creator>
    <dc:date>2020-11-29T22:16:46Z</dc:date>
    <item>
      <title>Regarding IEEE 1588</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-IEEE-1588/m-p/1190216#M14023</link>
      <description>&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;I have read this paper which was implemented in coldfire, Here they didn't mentioned about the switch what switch they are using here. Do we need ptp support switch or normal ethernet switch is enough to run the ptp(ieee 1588)&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 27 Nov 2020 09:49:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-IEEE-1588/m-p/1190216#M14023</guid>
      <dc:creator>Hariharan_Gandhi</dc:creator>
      <dc:date>2020-11-27T09:49:18Z</dc:date>
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    <item>
      <title>Re: Regarding IEEE 1588</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-IEEE-1588/m-p/1190580#M14026</link>
      <description>&lt;P&gt;Look at Figure&amp;nbsp; 4 in that document. Note the part that starts "&lt;SPAN&gt;Variable delay introduced &lt;/SPAN&gt;&lt;SPAN&gt;by the Network due to the &lt;/SPAN&gt;&lt;SPAN&gt;topology:". And that the protocol automatically handles this.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;BR /&gt;Tom&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 29 Nov 2020 22:16:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-IEEE-1588/m-p/1190580#M14026</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2020-11-29T22:16:46Z</dc:date>
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