<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: mcf54415 ddr2 clock speed</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677145#M13243</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Data Sheet gives a min/max range for SD_CLK from 100 to 250MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That wasn't what you were asking, but the programming you have seems to be achieving that goal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The diagram in "Figure 8-1. Device Clock Connections" and accompanying text in the Reference Manual is all you get. The description of "MISCCR2[DDR2CLK]" might help. It looks like the DDR module takes a double-frequency clock as input.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 12 May 2017 00:27:15 GMT</pubDate>
    <dc:creator>TomE</dc:creator>
    <dc:date>2017-05-12T00:27:15Z</dc:date>
    <item>
      <title>mcf54415 ddr2 clock speed</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677144#M13242</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;have a queston on ddr2 clock speed on mcf54415 custom board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What i actually so is :&lt;/P&gt;&lt;P&gt;- pll setup, i have&lt;/P&gt;&lt;P&gt;&amp;nbsp; fref = 30Mhz,&lt;/P&gt;&lt;P&gt;&amp;nbsp; refdiv = 0 (refdiv_divider = 1),&lt;/P&gt;&lt;P&gt;&amp;nbsp; cpu_clock configured to 240Mhz&lt;/P&gt;&lt;P&gt;&amp;nbsp; vco clock fixed at cpu_clock * 2,&lt;/P&gt;&lt;P&gt;&amp;nbsp; bus_clock at cpu_clock / 2&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- ddr2 (128MB) init / setup&lt;/P&gt;&lt;P&gt;- memtest, passes all 128MB&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- finally, DDR2 clock checked by scope, i see a syn at abt 240Mhz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Strangely, since i set that that ddr2 clock must come from VCO, with&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* use vco instead of cpu 2x clock for ddr clock */
&amp;nbsp;&amp;nbsp; &amp;nbsp;move.l&amp;nbsp;&amp;nbsp; &amp;nbsp;#MISCCR2, %a1
&amp;nbsp;&amp;nbsp; &amp;nbsp;move.w&amp;nbsp;&amp;nbsp; &amp;nbsp;#0xe01d, (%a1)
&amp;nbsp;&amp;nbsp; &amp;nbsp;/* use cpu clock */
&amp;nbsp;&amp;nbsp; &amp;nbsp;/* move.w&amp;nbsp;&amp;nbsp; &amp;nbsp;#0xa01d, (%a1) */&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;should i expect 480Mhz as ddr2 clock and 240 only if i set ddr2 clock coming from cpu clock ? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;angelo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 May 2017 10:48:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677144#M13242</guid>
      <dc:creator>angelo_d</dc:creator>
      <dc:date>2017-05-11T10:48:04Z</dc:date>
    </item>
    <item>
      <title>Re: mcf54415 ddr2 clock speed</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677145#M13243</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Data Sheet gives a min/max range for SD_CLK from 100 to 250MHz.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That wasn't what you were asking, but the programming you have seems to be achieving that goal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The diagram in "Figure 8-1. Device Clock Connections" and accompanying text in the Reference Manual is all you get. The description of "MISCCR2[DDR2CLK]" might help. It looks like the DDR module takes a double-frequency clock as input.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 May 2017 00:27:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677145#M13243</guid>
      <dc:creator>TomE</dc:creator>
      <dc:date>2017-05-12T00:27:15Z</dc:date>
    </item>
    <item>
      <title>Re: mcf54415 ddr2 clock speed</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677146#M13244</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;many thanks !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 May 2017 07:54:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/mcf54415-ddr2-clock-speed/m-p/677146#M13244</guid>
      <dc:creator>angelo_d</dc:creator>
      <dc:date>2017-05-29T07:54:23Z</dc:date>
    </item>
  </channel>
</rss>

