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    <title>ColdFire/68K Microcontrollers and ProcessorsのトピックRe: Regarding MCF5407 initialization</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-MCF5407-initialization/m-p/133444#M1255</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Prior to validating CS0, it will respond to all accesses as it is the "global chip-select".&amp;nbsp; Once it is validated, CS0 will only be activated for accesses that fall within the programmed address range.&amp;nbsp; Make sure that the debugger and your software are not attempting accesses outside the valid CS0 range after it is validated (i.e. after global CS is disabled).&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 28 Apr 2006 04:05:35 GMT</pubDate>
    <dc:creator>mnorman</dc:creator>
    <dc:date>2006-04-28T04:05:35Z</dc:date>
    <item>
      <title>Regarding MCF5407 initialization</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-MCF5407-initialization/m-p/133443#M1254</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;I am using MCF5407 in one of the projects. I am facing a strange problem while initializing the chip.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;We are using P&amp;amp;E ICDCFZ for debugging.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;After validating the Chipselect 0, the debugger will not be able to recongnize the processor. Only reset will bring me back to processor.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The sequence of initialization is as follows:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;1. Disable interrupts&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2. caches off, invalidate&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;3. clear all ACRs&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;4. Map internal SRAM&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;5. Map SIM module&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;6. Initialize PLLCR to 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;7. Disable watchdog&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;8. Disable all the chipselect other than 0 (V bit in CSMR(n) set to 0)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;9. program chipselect 0&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;10. Initialize the SDRAM&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The behaviour remains the same, without debugger connected..&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Has anyone faced similar kind of problem before?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In what ways enabling Global chipselect affect the processor?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Any pointer towards solution would be of great help.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks in advance,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Archana&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Apr 2006 22:02:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-MCF5407-initialization/m-p/133443#M1254</guid>
      <dc:creator>archana</dc:creator>
      <dc:date>2006-04-24T22:02:30Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding MCF5407 initialization</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-MCF5407-initialization/m-p/133444#M1255</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Prior to validating CS0, it will respond to all accesses as it is the "global chip-select".&amp;nbsp; Once it is validated, CS0 will only be activated for accesses that fall within the programmed address range.&amp;nbsp; Make sure that the debugger and your software are not attempting accesses outside the valid CS0 range after it is validated (i.e. after global CS is disabled).&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Apr 2006 04:05:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Regarding-MCF5407-initialization/m-p/133444#M1255</guid>
      <dc:creator>mnorman</dc:creator>
      <dc:date>2006-04-28T04:05:35Z</dc:date>
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