topic Re: 5213 IRQ1 problems in ColdFire/68K Microcontrollers and Processors

5213 IRQ1 problems

airswit — Sat, 14 Oct 2006 01:38:55 GMT

Hi everyone,

I have a keypad controller (MAX7348) hooked up to my 5213EVB through I2C. It seems to be programming right, and I have the IRQ output of the keypad controller connected to the edge port interrupt(level 1) pin. I hooked up a led to the same pin to see if the keypad controller is correctly signalling an interrupt on a keypress. the IRQ line is going low, but the processor is not going to the ISR for this level. Are there any differences between the IRQ1 pin and the other IRQ's, because I have several other external interrupt sources connected, and they all seem to be operating fine (with similar code for init, and the ISR functions themselves)? The processor does not jump to an illegal location or anything like that (it still runs the normal code fine...), it just does not execute the interrupt subroutine code! I have included some code of how i set up the interrut port, and the isr itself:

[code]
void setupInterrupts()
{
MCF_EPORT_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA1_BOTH
| MCF_EPORT_EPPAR_EPPA3_RISING
| MCF_EPORT_EPPAR_EPPA4_RISING
| MCF_EPORT_EPPAR_EPPA5_RISING
| MCF_EPORT_EPPAR_EPPA6_FALLING
| MCF_EPORT_EPPAR_EPPA7_LEVEL; //pin6 changed (see if it'll work)

/* MCF_INTC_ICR21 = 0
| MCF_INTC_ICR_IP(3)
| MCF_INTC_ICR_IL(1); //set priorities
MCF_INTC_IMRL &= ~ MCF_INTC_IMRL_MASK21;
*/

/* mcf5xxx_set_handler(64 + 1, key_handler);
mcf5xxx_set_handler(64 + 3, power_down);
mcf5xxx_set_handler(64 + 4, sw1_handler);
mcf5xxx_set_handler(64 + 5, sw2_handler);
mcf5xxx_set_handler(64 + 6, zero_cross);
mcf5xxx_set_handler(64 + 7, abort_handler);
mcf5xxx_set_handler(64 + 21,delay_handler);
mcf5xxx_set_handler(64 + 55,quad_handler); //PIT0 interrupt
*/
//check out vectors.s for ^^ definitions (don't want to use the 200k runtime library!!!
mcf5xxx_irq_enable(); //enable interrupts
}
[/code]

[code]
__interrupt__ void key_handler(void)
{
uint8 keypress = 0x40;

TURN_OFF_DISPLAY_PWR;
while(keypress & 0x40)
{
keypress = I2CreceiveByte(KEYSCAN_FIFO,KEYSCAN_ADDR); // the key
interpretKey(keypress); //what do we do???
}
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1; //clear the interrupt

}

[/code]

from sysinit.c:
[code]

void mcf5213_allow_interrupts(void)
{
/*
* Allow interrupts from ABORT, SW1, and SW2 (IRQ[4,5,7])
*/

/* Enable IRQ signals on the port */
MCF_GPIO_PNQPAR = 0
| MCF_GPIO_PNQPAR_IRQ1_IRQ1
| MCF_GPIO_PNQPAR_IRQ3_IRQ3
| MCF_GPIO_PNQPAR_IRQ4_IRQ4
| MCF_GPIO_PNQPAR_IRQ5_IRQ5
| MCF_GPIO_PNQPAR_IRQ6_IRQ6
| MCF_GPIO_PNQPAR_IRQ7_IRQ7;

/* Set EPORT to look for rising edges */
MCF_EPORT_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA1_FALLING
| MCF_EPORT_EPPAR_EPPA3_RISING
| MCF_EPORT_EPPAR_EPPA4_RISING
| MCF_EPORT_EPPAR_EPPA5_RISING
| MCF_EPORT_EPPAR_EPPA6_RISING
| MCF_EPORT_EPPAR_EPPA7_RISING;

/* Clear any currently triggered events on the EPORT */
MCF_EPORT_EPIER = 0
| MCF_EPORT_EPIER_EPIE1
| MCF_EPORT_EPIER_EPIE3
| MCF_EPORT_EPIER_EPIE4
| MCF_EPORT_EPIER_EPIE5
| MCF_EPORT_EPIER_EPIE6
| MCF_EPORT_EPIER_EPIE7;

/* Enable interrupts in the interrupt controller */
MCF_INTC_IMRL &= ~(0
| MCF_INTC_IMRL_MASK1
| MCF_INTC_IMRL_MASK3
| MCF_INTC_IMRL_MASK4
| MCF_INTC_IMRL_MASK5
| MCF_INTC_IMRL_MASK6
| MCF_INTC_IMRL_MASK7
| MCF_INTC_IMRL_MASKALL
| MCF_INTC_IMRL_MASK13);
}
[/code]

Re: 5213 IRQ1 problems

mjbcswitzerland — Sun, 15 Oct 2006 19:38:59 GMT

Hi Airswit

There is a difference in the PNQPAR register since the IRQ1 has to be configured for a quad function rather than dual function (as for other IRQ lines).

Therefore check that the value is being set correctly for Primary function. (I believe that these pins all default to IRQ inputs after a reset and so possibly need no configuration at all).

Regards

Mark Butcher
www.mjbc.ch / www.uTasker.com

Re: 5213 IRQ1 problems

airswit — Mon, 16 Oct 2006 08:49:04 GMT

well, if you look at the enable_interrupts function (in sysinit.c w/ default stationary), it uses the macro for IRQ1, and it looks correct (0x01 for that pin), and my setupInterrupts function, the eport registers are set. i can't seem to figure out why it is not interrupting..i hooked it to another irq line (irq4, temporarily), and it interrupted just fine.

any other thoughts on what is going on?

Re: 5213 IRQ1 problems

DrSeuss — Thu, 19 Oct 2006 11:34:01 GMT

You might look at your vector definitions, if your are hard coding them in flash I recommend:

vector40: .long _irq_handler40 /* EPF0 - not available*/
vector41: .long _irq_handler41 /* EPF1 */
vector42: .long _irq_handler42 /* EPF2 */
vector43: .long _irq_handler43 /* EPF3 */
vector44: .long _irq_handler44 /* EPF4 */
vector45: .long _irq_handler45 /* EPF5 */
vector46: .long _irq_handler46 /* EPF6 */
vector47: .long _irq_handler47 /* EPF7 */

Note that irq0 is not available. I have seen many definitions (header files) that miss this and all vectors are shifed up by one. I am trying to clear this up in the docs. Also note that irq1 is the lowest prioitiy interrupt if ANY other is active it will not be serviced.

Re: 5213 IRQ1 problems

airswit — Thu, 19 Oct 2006 12:52:12 GMT

I am hard coding the isr names in the vectors.s file. I am also locating them in the correct location (64+(irq#)), as all the other ones are working just fine. I know that it is not the other IRQ levels that are causing this code to not be run, because i have a main loop sending data to a d/a, and that is executing, therefore if regular code can run, irq level 1 should be able to interrut that normal program execution. anyway, i have abandoned IRQ1, and have used IRQ2, and it is working fine now! Thanks for the suggestions, anyway...

Re: 5213 IRQ1 problems

M_ttferrari — Tue, 11 May 2010 22:42:06 GMT

Sorry by re-open this old topic

But I have the same problem with IRQ1 and I don't know how I can fix it. All my others IRQs work fine using the same IRQ configuration.

Matt

Re: 5213 IRQ1 problems

mjbcswitzerland — Thu, 13 May 2010 22:20:48 GMT

Hi Matt

I just tested IRQs 1, 4, 5 and 7 on an M5213EVB. All worked as expected.

The only difference in the code to handle IRQ1 configuration is the following:

                if (ucIRQ_bit == 1) {                                    // special case IRQ1 pin has quad function
                    PNQPAR &= ~0x03;
                    PNQPAR |= 0x01;
                }
                else {
                    PNQPAR |= (0x01 << ucIRQ_bit);                       // other pins have dual function
                }

Since all pins default to their IRQ configuration these are however no usually needed.

If you want to verify your HW I have attached the file that I just tested so that you can load it to your board. It should run on any board with 8MHz crystal and uses UART0 at 115200 Baud. When the corresponding edge on these pins is detected it writes a message to this output.

You can get complete code at http://www.utasker.com/Licensing/request.html

Regards

Mark

www.uTasker.com

Re: 5213 IRQ1 problems

M_ttferrari — Fri, 14 May 2010 03:50:06 GMT

Ok thank you by your response Mark!