MCF5485 FEC inverted CRC

alexeyminkov — Thu, 18 Sep 2014 10:31:39 GMT

Good afternoon. Information on MCF5485.

FEC0 through MII is connected to the transmitter KSZ8051 next is plug on itself.

Did initialization FEC0 below is attached.

Made a simple program written in the FIFO and the reader.

Look at the results, the data came, and on a bad CRC.

The coup is at the stage of issuance.

How to get rid of this?

I.e. If I have a personal computer, give the package, everything is fine.

And when trying to transfer from the PC, the FEC0 CRC error.

In p. "31.4.2.2 Transmit Frame Control Word (TFCW) indicates that the 1 Transmit the CRC sequence inverted after the last data bye (regardless of the TC value)» how to get rid of this?

move.l #0x80009024,a1	//#ECR0 Сброс всех регистров FEC0
move.l #0x00000001,(a1)
nop
nop

move.l #0x80009008,a1			//#EIMR0
move.l #0x00000000,(a1)		//Запретить все прерывания fec0

move.l #0x80009004,a1	//#EIR0 Очистить регистр прерываний FEC0
move.l #0xffffffff,(a1)


move.l #0x80009144,a1			//#FECTFWR0 Настроить Watermark: кол-во байт в FIFO, после
move.l #0x7,(a1)			//которого начнется передача (512)=64*(7+1)

move.l #0x80009118,a1			//#IAUR0 Индив.адр.назначения
move.l #0x0,(a1)				//Старшие 32 разряда

move.l #0x8000911c,a1			//IALR0 Младшие 32 разряда
move.l #0x0,(a1)

move.l #0x80009120,a1			//#GAUR0 Групп.адр.назначения
move.l #0x0,(a1)				//Старшие 32 разряда

move.l #0x80009124,a1

//#GALR0 Младшие 32 разряда

move.l #0x0,(a1)

move.l #0x800090e4,a1	//#PALR0 Физический адр.назначения
move.l #0x0,(a1)		//Младшие 32 разряда

move.l #0x800090e8,a1	//#PAHR0 Старшие 16 разрядов
move.l #0x8808,(a1)

move.l #0x80009084,a1	//#RCR0	Receive Ctrl: max frame lenght=1518 (0x5ee)
move.l #0x05ee000c,(a1)	//PROM=1 (all frames); MII_MODE=1

	move.l #0x800090c4,a1		//#TCR0	Transmit Ctrl: full duplex enable
	move.l #0x4,(a1)

	move.l #0x80009064,a1		//#MIBC0 MIB logic halt
	move.l #0xc0000000,(a1)

	move.l #0x80009200,a1		//#RMON_T_DROP0 Инициализация счетчиков
fe10:
	move.l #0x00000000,(a1)+
	cmpa.l #0x80009278,a1
	bne	fe10

	move.l #0x80009280,a1		//#RMON_R_DROP0
fe20:
	move.l #0x00000000,(a1)+
	cmpa.l #0x800092e4,a1
	bne	fe20

	move.l #0x80009064,a1		//#MIBC0 MIB logic enable
	move.l #0x00000000,(a1)

	move.l #0x800091c4,a1		//#FECFRST0 Reset FIFOs
	move.l #0x03000000,(a1)
	move.l #0x00000000,(a1)
	nop
	nop
	nop

	move.l #0x800091ac,a1			//#FECTFCR0 Transmit: Frame mode enable;
	move.l #0x09340000,(a1)			//last transfer granularity = 1; FIFO underflow mask

	move.l #0x8000918c,a1			//#FECRFCR0 Receive: аналогично transmit
	move.l #0x09140000,(a1)

	move.l #0x800091c8,a1			//#FECCTCWR0 CRC enable
	move.l #0x03000000,(a1)

	move.l #0x800091b8,a1			//#FECTFAR0 Trans Alarm - 1023
	move.l #0x200,(a1)//512

	move.l #0x80009198,a1			//#FECRFAR0 R Alarm - уст.,когда осталось 768 байт
	move.l #0x200,(a1)//512

	move.l #0x80009024,a1
	move.l #0x00000002,(a1)

	move.l #0x80009044,a1
	move.l #0x000000B0, (a1)

	move.l #0x80009040,a1			//4
	move.l #0x509201E1, (a1)

	move.l #0x80009040,a1			//1
	move.l #0x50822100, (a1)

Re: MCF5485 FEC inverted CRC

TomE — Fri, 19 Sep 2014 06:21:24 GMT

I think your mistake is this:

move.l #0x800091c8, a1 //#FECCTCWR0 CRC enable

move.l #0x03000000, (a1)

"CRC Enable" is 0x02000000 and not 0x03000000

You're also setting the TFCW (Transmit Frame Control Word Enable) bit, which is telling the transmitter to read an EXTRA 32-bits from the FIFO. One of the bits in that extra word is "transmit the wrong CRC". Don't set the TFCW bit in the first register and it shouldn't transmit the bad CRC.

Tom

Re: MCF5485 FEC inverted CRC

TomE — Sun, 21 Sep 2014 12:38:27 GMT

The Ethernet controller in the MCF5485 looks to be a derivative of the one in the MPC5200.

There is driver code here for that chip:

http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/

However, the MPC5200 uses a very complicated "Bestcom" DMA controller, which looks to be different to the one in the MCF5485.

The MPC5200 manual documents a "Table 14-38. FEC Transmit FSM Register" which is similar to the "31.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTC)" one in the MCF5485. In the MPC part the register enables (separately) Generating and Appending the CRC. It looks like the "14.9.3.2 Transmit Frame Control Word" is compulsory for this chip, and that controls on a per-frame basis whether the CRC is transmitted, and if it is good or bad. In the MCF5485 it looks like the FECCTC register controls whether the TFCW is to be used, so it seems to be optional.

If the manual is wrong and it isn't optional, you need to (somehow) send a valid TFCS as part of the transmit stream.

Why are you writing in assembly? If you wrote in C you should at least have header files defining the registers and the contents already available.

Tom

Re: MCF5485 FEC inverted CRC

alexeyminkov — Mon, 22 Sep 2014 05:14:17 GMT

Thank you very much Tom Evans.

I figured out.

To record the "WFR bit"/"WCTL bit" registry FEC "the Transmit FIFO Control Register (FECTFCR)" and then write "data"/"Control Word".

Now everything works.

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