ColdFire/68K Microcontrollers and ProcessorsのトピックRe: DMA Timer

DMA Timer

salman83 — Mon, 02 Jun 2014 11:11:18 GMT

Hi,

I am using DMA timers. For some unknown reason, i am keep getting Transmit Frame Interrupt even this interrupt is disabled.

I am attaching the source code for the timer.

Regards.

Original Attachment has been moved to: timer.c.txt.zip

Original Attachment has been moved to: timer.h.txt.zip

Re: DMA Timer

TomE — Wed, 04 Jun 2014 07:33:19 GMT

What CHIP are the DMA Timers in? Which CPU are you using?

Which peripheral is giving you the supposed "Transmit Frame Interrupt"? The DMA timers don't do this.

Is it a UART Transmit interrupt, an Ethernet Transmit interrupt, a QSPI Transmit interrupt a CAN Transmit interrupt or something else?

In case you've got that wrong you should provide the actual interrupt vector you're getting, so we can cross-check in case that's your mistake.

After you've written your question, you should read it as if you were someone else before posting it. Ask yourself if you've provided enough information for anyone ELSE to be able to understand what you're doing.

Tom

Re: DMA Timer

salman83 — Wed, 04 Jun 2014 08:11:57 GMT

Sorry about that. I should have written the whole info.

I am using MCF52259.

This is how initialized the supervisor register

	// DMA Timer 0-1 : Read/Write (Supervisor/User mode)
	MCF_SCM_PACR6 = 0x66;

	// DMA Timer 2-3 : Read/Write (Supervisor/User mode)
	MCF_SCM_PACR7 = 0x66;

This is how I enabled the interrupts

	// Enable DMA Timer#0 interrupt
	MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK19;

	// Enable DMA Timer#1 interrupt
	MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK20;

	// Enable DMA Timer#2 interrupt
	MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK21;

	// Enable DMA Timer#3 interrupt
	MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_INT_MASK22;

Here is the list of interrupt controller #0 registers state when Transmit Frame Interrupt is called

IPRH0		0x00200000
IPRL0		0x00780000
IMRH0		0xFFDFFFFF
IMRL0		0xFF87FFFE
INTFRCH0	0x00000000
INTFRCL0	0x00000000
IRLR0		0x10
IACKLPR0	0x45
ICR001		0x08
ICR002		0x10
ICR003		0x18
ICR004		0x20
ICR005		0x28
ICR006		0x30
ICR007		0x38
ICR008		0x00
ICR009		0x00
ICR010		0x00
ICR011		0x00
ICR012		0x00
ICR013		0x00
ICR014		0x00
ICR015		0x00
ICR016		0x00
ICR017		0x00
ICR018		0x00
ICR019		0x25
ICR020		0x25
ICR021		0x25
ICR022		0x25
ICR023		0x00
ICR024		0x00
ICR025		0x00
ICR026		0x00
ICR027		0x00
ICR028		0x00
ICR029		0x00
ICR030		0x00
ICR031		0x00
ICR032		0x00
ICR033		0x00
ICR034		0x00
ICR035		0x00
ICR036		0x00
ICR037		0x00
ICR038		0x00
ICR039		0x00
ICR040		0x00
ICR041		0x00
ICR042		0x00
ICR043		0x00
ICR044		0x00
ICR045		0x00
ICR046		0x00
ICR047		0x00
ICR048		0x00
ICR049		0x00
ICR050		0x00
ICR051		0x00
ICR052		0x00
ICR053		0x24
ICR054		0x00
ICR055		0x00
ICR056		0x00
ICR057		0x00
ICR058		0x00
ICR059		0x00
ICR060		0x00
ICR061		0x00
ICR062		0x00
ICR063		0x00
SWIACK0		0x57
L1IACK0		0x18
L2IACK0		0x18
L3IACK0		0x18
L4IACK0		0x57
L5IACK0		0x18
L6IACK0		0x18
L7IACK0		0x18

Rest of the DMA Timer timer source code I already attached in my previous post.

Regards.

Re: Re: DMA Timer

TomE — Wed, 04 Jun 2014 23:45:29 GMT

> > Is it a UART Transmit interrupt, an Ethernet Transmit interrupt, a QSPI Transmit interrupt a CAN Transmit interrupt or something else?

> Here is the list of interrupt controller #0 registers state when Transmit Frame Interrupt is called

You still haven't said which "Transmit Frame" interrupt, so I guess I have to try and ask the machine:

IPRH0 0x00200000 Bit 21, interrupt 53 - USB Interrupt

IPRL0 0x00780000 Bits 19, 20, 21, 22 - DMA Timer Interrupts

Is that the one you're getting? You didn't say you had USB Interrupts enabled and active.

Anyway, I can see obvious and serious problems with your interrupt controller programming.

You've made a common mistake. You've got the IDENTICAL programming for the ICRnx registers for the DMA Timers - all 0x25. Likewise for the Level Interrupts. Quoting from the chapter on the Interrupt Controller in the Reference Manual:

16.3.6 Interrupt Control Registers (ICRnx)

It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping

level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined

behavior.

This happens a lot:

Re: MCF5235 Interrupt Vector 191

Re: Guidance on tracking down spurious interrupts

Re: Wrong interrupt handler being called after period of normal operation (MCF5235)

Re: CFV2 vector 125??? (vector or'ing?)

Re: Unhandled Interrupt vector 0x9f (159)

5223X Interrupt Controller -- setting levels/priorities

Re: Cpu_Interrupt while using Processor expert 52221DEMO

Re: Question about coldfire V2 interrupt priority

Re: Confusion on priority levels with exception handlers

Tom