ColdFire/68K Microcontrollers and Processors中的主题 Debugging JF128 with Slow Clock (32KHz)

Debugging JF128 with Slow Clock (32KHz)

pgo — Sat, 01 Mar 2014 11:16:57 GMT

Dear All,

I have been unable to debug a very basic program on a MCF51JF123 when operating on the 32kHz internal reference clock.

Can anyone tell me if it is possible to debug at this slow a speed using P&E Multilink or OSBDM or is this a limitation of the debug interface on the JF128 device.

I am able to debug programs on the Kinetis devices at a similar speed.

bye

Re: Debugging JF128 with Slow Clock (32KHz)

TomE — Fri, 07 Mar 2014 11:35:06 GMT

After searching in thie Forum and finding nothing I searched P&E's ColdFire Forum and got a match on a search for "32 kHz":

Aug 17, 2009 V1QE128 debugging clock issue

P&E Microcomputer Systems

www.pemicro.com/forums/forum.cfm?forum_id=4&forum_topic_id=3437

Unfortunately their Forum is broken and clicking on the link the Search found results in "Topic does not exist at PEMicro". I've complained to the site (after fighting two more sets of bugs with their Forum) so there's a chance they might fix this and the topic might turn up eventually.

As you're a P&E Customer, you should log a Service Request with them, or phone them up.

Tom

Re: Debugging JF128 with Slow Clock (32KHz)

yibbidy — Mon, 10 Mar 2014 00:12:20 GMT

I've not used this part but it looks like the part is able to do this (from the ref man):

18.4.3.3 BDM in Run and VLPR Mode

If the MCU is unsecure and BDM mode is enabled, then the MCU can be fully debugged using the BDM in RUN and VLPR modes. If XCSR[ENBDM] = 0, before entering active BDM mode, the host must write XCSR[ENBDM] = 1 before sending a BACKGROUND command.

Have you checked which clock you are using for the BDM clock:

21.4.6 MCG Background Debug Controller Clock

The MCG Background Debug Controller Clock (MCGBDCCLK) provides a clock source to the Background Debug Controller (BDC). This clock is driven by either the SYSCLK or the 4 MHz internal reference clock (IRC), as selected by the XCSR[CLKSW] bit in the V1 ColdFire debug module.

Shaun

Re: Debugging JF128 with Slow Clock (32KHz)

pgo — Mon, 10 Mar 2014 08:51:03 GMT

Hi Shaun,

That was my interpretation of the manual but I'm unsure if it is possible to set the BDM Clock source in the debugger interface for the P&E Interface - I will have to check this.

Doing so in USBDM results in loss of connection - possibly because of the large disparity between the BDM ALT clock ~10MHz and the Bus clock.

bye

Re: Debugging JF128 with Slow Clock (32KHz)

yibbidy — Tue, 11 Mar 2014 00:31:42 GMT

I've not seen anywhere for the P&E interface where the clock source or speed can be set. Tom's suggestion to contact P&E might be the best chance.

I know that it is not possible to debug the QE128 part using the internal 32kHz clock. I suspect that this is because the QE uses the ICS clock module and the JF uses the MCG clock module, even though they both use the same BDM module.

I'll be interested to see how you get on.

Shaun