QSPI single transfer setup (MFC5272)

louis_springbok — Tue, 21 May 2013 15:17:27 GMT

I'm trying to receive an 8 bit value from a tlv0831 (datasheet here: http://www.ti.com/lit/ds/symlink/tlv0831.pdf) and the value that I keep receiving goes back and forth between 63 and 191. I believe I'm reading the datasheet correctly in that I just need to send the A/D a dummy value (0x00) and I will get back only the most significant byte.

uint8 GetBatteryLevel( void ) {   //uint8 battery_level;   vuint16 test;    //SPI Chip Select MUX control pins   MCF5272_GPIO_PBDAT = MCF5272_GPIO_PBDAT   & ~MCF5272_GPIO_PB9_SPICS_CTRL0   & ~MCF5272_GPIO_PB12_SPI_CS_CTRL1;    /* Set up QMR mode register */   MCF5272_QSPI_QMR = 0   | MCF5272_QSPI_QMR_MSTR /* Master Mode Enable     */   | MCF5272_QSPI_QMR_DOHIE /* High Impedance         */   | MCF5272_QSPI_QMR_BITS(8) /* 8 bits transfer size  */   | MCF5272_QSPI_QMR_CPOL /* Inactive state logic 0 */   | MCF5272_QSPI_QMR_CPHA /* Captured '0' */   | MCF5272_QSPI_QMR_BAUD(250); /* 250k Baud rate      */   /* Set up QDLYR delay register    */   MCF5272_QSPI_QDLYR = 0x0D01;    /* Set up QIR interrupt register - Clear all Interrupts */   MCF5272_QSPI_QIR = 0xD00D;    /* QAR address register - Command RAM 0x20 */   MCF5272_QSPI_QAR = 0x0020;     /* Set up QDR data register - CS3 */   //SPI Chip Select MUX enable   MCF5272_GPIO_PADAT = MCF5272_GPIO_PADAT   & ~MCF5272_GPIO_PA7_QSPI_CS_MUX_CTRLER;    /* Set up QWR wrap register */   MCF5272_QSPI_QWR = 0 | MCF5272_QSPI_QWR_CSIV;     /* Select first transmit RAM entry */   MCF5272_QSPI_QAR = 0x0000;     /* Transmit - Read 1 word */   MCF5272_QSPI_QDR = 0x00;    /* Set up a queue beginning at entry 0 */   MCF5272_QSPI_QWR = MCF5272_QSPI_QWR | 0x0800;     /* Enable QSPI module  */   MCF5272_QSPI_QDLYR = MCF5272_QSPI_QDLYR | 0x8000;     /* Wait to finish transfer */   while((MCF5272_QSPI_QIR & 0x0001) == 0) ;     /* Select the first receive RAM entry */   MCF5272_QSPI_QAR = 0x0010;    /* Read from first receive RAM entry */   test = (MCF5272_QSPI_QDR & 0x00FF);    /* Disable QSPI module  */   MCF5272_QSPI_QDLYR = 0   | MCF5272_QSPI_QDLYR   & 0x7FFF;    //SPI Chip Select MUX disable   MCF5272_GPIO_PADAT = MCF5272_GPIO_PADAT   | MCF5272_GPIO_PA7_QSPI_CS_MUX_CTRLER;    //SPI Chip Select MUX control pins reset   MCF5272_GPIO_PBDAT = MCF5272_GPIO_PBDAT   | MCF5272_GPIO_PB9_SPICS_CTRL0   | MCF5272_GPIO_PB12_SPI_CS_CTRL1;      return (uint8)test; }

Re: QSPI single transfer setup (MFC5272)

TomE — Tue, 21 May 2013 23:31:02 GMT

Easy.

ADCs need time to convert. The more complicated ones need to be commanded to perform a conversion on one SPI sequence with the data to be read back on the next one. You're lucky with this chip as it returns the data in one SPI cycle. But it still needs time to work.

Have a closer look at the "Sequence of Operations" on Page 4 of the TI data sheet.

The bit numbers go from 1 to TEN, not 1 to eight.

So change your code to "MCF5272_QSPI_QMR_BITS(10)".

Check CPHA as well. I'm pretty sure it is correct, but compare the QSPI and TI timing diagrams.

If this answers your question, please mark it "Answered".

Tom

Re: QSPI single transfer setup (MFC5272)

louis_springbok — Wed, 22 May 2013 14:52:36 GMT

Thank you very much Tom. The problem was making "MCF5272_QSPI_QMR_BITS(10)" and the CPHA was correct.

Louis

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QSPI single transfer setup (MFC5272)

Re: QSPI single transfer setup (MFC5272)

Re: QSPI single transfer setup (MFC5272)