topic Re: Configuring RAMBAR register in ColdFire/68K Microcontrollers and Processors

Configuring RAMBAR register

salman83 — Thu, 09 May 2013 12:22:47 GMT

Hi,

I was reading the documentation for MCF52254. While configuring the RAMBAR register, I do not understand the meaning of bit 5.

RAMBAR

Address Space Masks

C/I = CPU space/interrupt acknowledge cycle mask

Also, for FLASHBAR register, is it OK to enable the Address fetch speculation (AFS) bit 6. I have read from other posts that it is creates problem when enabled and it is a bug acknowledged by Freescale.

Any help will be highly appreciated.

Regards.

Re: Configuring RAMBAR register

TomE — Fri, 10 May 2013 03:06:35 GMT

> I do not understand the meaning of bit 5.

You really need to have followed every Freescale/Motorola part from the 68000 on to understand what the "Address Spaces" mean and what they're used for.

You don't need to know.

The manual says:

Table 12-2. RAMBAR Field Descriptions (continued)

5–1 C/I, SC, SD, UC, UD

These bits are useful for power management as detailed in Section

12.3.2, “Power Management.” In most applications, the C/I bit is set

You can believe the above advice. You don't want the SRAM responding to interrupt cycles!

> Also, for FLASHBAR register, is it OK to enable the Address fetch speculation

The Chip Errata document (MCF52259DE.pdf) doesn't list that as a problem for this chip.

> have read from other posts that it is creates problem when enabled

> and it is a bug acknowledged by Freescale.

I can only find this one which indicates you don't have a problem. What did you find?

https://community.freescale.com/message/50265#50265

I received confirmation from freescale that the "speculaton bug has been fixed in the MCF5225X".

This means that the workaround is no longer needed for this chip.

Tom

Re: Configuring RAMBAR register

Monica — Tue, 14 May 2013 23:05:08 GMT

Hello Salman!

Were those hints helpful?

Please keep us posted!

Monica