topic exception stack and TLB's in ColdFire/68K Microcontrollers and Processors

exception stack and TLB's

degan — Sat, 15 Apr 2006 01:38:57 GMT

Is it possible to define a TLB for the exception stack or must the exception stack always be in miss-proof memory?

If I can, what happens if a stack overflow/underflow occurs while handling an exception? What I am seeing is TLB miss after TLB miss and the stack just walks off the end of memory.

Thanks,

Doug

Re: exception stack and TLB's

mnorman — Fri, 28 Apr 2006 03:59:53 GMT

Is the TLB miss occuring on an instruction fetch (fault status 0101)? It sounds like the access to either the vector table or the exception routine is causing a miss that results in a recursive miss-exception loop.

Re: exception stack and TLB's

degan — Wed, 07 Jun 2006 22:16:39 GMT

No, the miss is happening when the interrupt stack is blown when pushing data onto it. We would like to setup guard pages around the interrupt stack to cleanly recover from overflowing it. I haven't been able to see how to do that.