Ethernet Rx interrupt handling in FNET Stack

Neerajjaini — Thu, 09 Jun 2011 15:36:07 GMT

Hello,

We are using FNET Stack for MCF52259 based application.

Some information is required to optimize my application, I need to clarify following.

1.) Multiple Ethernet RX buffer and Tx Buffer are used. Why it is required and its benefit?

2.) After doing some brief study of FNET stack,it appears that after receiving the Ethernet Frame some software interrupt is generated for ARP and IP.

Please know me , How software interrupt is executing while Vector number of SW interrupts are out of Vector table or there is other mechanism used to slice f Ethernet Receive frame interrupt.

Re: Ethernet Rx interrupt handling in FNET Stack

butok — Mon, 13 Jun 2011 17:32:11 GMT

Hi Neerajjaini,

>>Multiple Ethernet RX buffer and Tx Buffer are used. Why it is required and its benefit?

It is enough to have two TX buffers (defined by FNET_CFG_CPU_ETH_TX_BUFS_MAX). While FEC sends frame from one buffer, the FEC driver may fill the second one.

On practice, two RX buffers can be enough (defined by FNET_CFG_CPU_ETH_RX_BUFS_MAX), but you can set it to bigger value to avoid dropping of received frames if an application is not so fast to handle them on time.

>>2.) after receiving the Ethernet Frame some software interrupt is generated for ARP and IP.

These “SW interrupts” are not "real" interrupts. They are functions that use functionality of the FNET Interrupt Scheduler and critical code blocking mechanism.

>>How software interrupt is executing while Vector number of SW interrupts

They are not registered in CPU vector table (as they are not connected to HW), they are called by SW.

BTW: You can send any FNET improvements/fixes (if any) directly to Andrey.Butok@freescale.com

Thank you,

Andrey Butok

topic Ethernet Rx interrupt handling in FNET Stack in ColdFire/68K Microcontrollers and Processors

Ethernet Rx interrupt handling in FNET Stack

Re: Ethernet Rx interrupt handling in FNET Stack