<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>ColdFire/68K Microcontrollers and Processors中的主题 Re: Coldfire 52234 FEC issue</title>
    <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Coldfire-52234-FEC-issue/m-p/213127#M10605</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;How many frame are you able to receive before the FEC locks up?&amp;nbsp; I might be your release_RxBuffer_descr()&amp;nbsp;&amp;nbsp;function that's in cause.&amp;nbsp; Make shure the Wrap bit stays set to one.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Francois&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 11 Jan 2009 01:50:16 GMT</pubDate>
    <dc:creator>francois_boucha</dc:creator>
    <dc:date>2009-01-11T01:50:16Z</dc:date>
    <item>
      <title>Coldfire 52234 FEC issue</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Coldfire-52234-FEC-issue/m-p/213126#M10604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;SPAN&gt;Hi everybody,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm wondering about a strange behaviour of the 52234's FEC. I have&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;set up the FEC to handle only one receive BD which buffer size is&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2048 bytes. In presence of a heavily loaded network I get a FEC lock&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;even if I always free the unique receive BD every time its E bit is set&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;to 0 by the FEC DMA engine. When I say FEC lock I intend that no&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;more RXF interrupts are rised.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I suspect the FEC locks because may happen that the receive FIFO is&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;full and there are no free receive BDs to write in the OV bit. Is my&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;assumption correct ? Can you explain me this FEC behaviour ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Best Regards&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/Alessandro&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Dec 2008 07:37:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Coldfire-52234-FEC-issue/m-p/213126#M10604</guid>
      <dc:creator>Alessandro</dc:creator>
      <dc:date>2008-12-31T07:37:39Z</dc:date>
    </item>
    <item>
      <title>Re: Coldfire 52234 FEC issue</title>
      <link>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Coldfire-52234-FEC-issue/m-p/213127#M10605</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;How many frame are you able to receive before the FEC locks up?&amp;nbsp; I might be your release_RxBuffer_descr()&amp;nbsp;&amp;nbsp;function that's in cause.&amp;nbsp; Make shure the Wrap bit stays set to one.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Francois&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 11 Jan 2009 01:50:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/Coldfire-52234-FEC-issue/m-p/213127#M10605</guid>
      <dc:creator>francois_boucha</dc:creator>
      <dc:date>2009-01-11T01:50:16Z</dc:date>
    </item>
  </channel>
</rss>

