topic Traces under Isolated Gate Driver in Powertrain and Electrification Analog Drivers

Traces under Isolated Gate Driver

travisalexander — Thu, 02 Sep 2021 20:35:06 GMT

Hey Travis,

Could you advise on this question?

I've seen that your competitors will state in their datasheets that no traces or planes should be placed underneath the isolation area. Is this also the case for the NXP part?

Jack Jamieson

M: (419) 261-5225

Re: Traces under Isolated Gate Driver

travisalexander — Sat, 29 Feb 2020 07:14:24 GMT

Hi Jack,

Yes this is the case--no traces under the IC.

The reason you can't have traces under the gate driver is to meet creepage and clearance isolation requirements separating the HV gate from the LV MCU side.

We put this information in the GD3100 app note (AN12357, section 9.1).

Regards,

Travis