S32-pinctrl (Zephyr)

rfpereiro — Fri, 12 Jul 2024 12:50:49 GMT

Hi NXP-community,

we are porting some SW to an S32ZE Board using Zephyr (v3.6.0). Setting up some flexcan interfaces using NXP-RTD (RTD Flexcan S32ZE AUTOSAR R21-11 RTD 1.0.0 P12) we realized that the pin configuration does not work properly when using instances of the SIUL2_3.

The macro NXP_S32_PINMUX (zephyr\include\zephyr\dt-bindings\pinctrl\nxp-s32-pinctrl.h) truncates the IMCR-idx values above 512 which are required by the driver to determine wich SIUL2 instance shall be used as base.

Besides this, we saw that the pinctrl mux are defined in a way that when the pins are initialized by the SIUL2-driver the MSCR register of the given is not initialized.

In the attached photo we are configuring the pin, taking the siul2_0 as base.

PB7_CAN_1_RX NXP_S32_PINMUX(0, 23, 0, 513, 2)

before it was as shown below, which was taking the siul2_3 as base for the set of MSCR leading to a not synchronized flexcan instance.
PB7_CAN_1_RX NXP_S32_PINMUX(3, 23, 0, 513, 2)

Are we overseeing something here or do we need to really correct the macro+siul2-idx instances in the zephyr code?

Thanks in advance!
Roberto

Zephyr ProjectのトピックS32-pinctrl (Zephyr)

S32-pinctrl (Zephyr)