topic Re: KW45 Power Management hardware Design in Wi-Fi® + Bluetooth® + 802.15.4

KW45 Power Management hardware Design

tomaru — Mon, 18 Aug 2025 00:45:10 GMT

Dear NXP,

I am trying to make a custom board using KW45 MCU.

I have few questions -

For all the power circuits I am referring document AN13831 -KW45/K32W148 - Power Management Hardware and KW45/K32W1 HARDWARE DESIGN RECOMMENDATION guide.

In both documents the diagrams for the KW45 power lines to cores confused me.

Document I - AN13831 -KW45/K32W148 - Power Management Hardware

Document II - K32W1 HARDWARE DESIGN RECOMMENDATION guide

Query - How are the cores power lines connected? Are they internally connected, or we need to do it through external circuit?

Example - LDO-CORE Input in both Diagram is provided from VDD_LDO_CORE and its output in Document I can be seen as internally connected to VDD_CORE while in document II it is shown as externally connected.
Such queries exist for other supply as well like -
1. VDD_RF and VDD_PA_2.4G - Where do supply go from and to where? From VDD_RF to VDD_PA or vice versa.
2. From LDO_SYS to VDD_SYS ? Is the wire internal or external ?

BR,
Tomaru

Re: KW45 Power Management hardware Design

luis_maravilla — Mon, 18 Aug 2025 18:31:23 GMT

Hello Tomaru,

Could you help us confirm what configuration are your using? As I see DCDC Buck mode in the image. [Bypass mode, DC-DC Buck mode,PMIC mode, DC-DC mode controlled with Smart Power Switch]

In the block diagram, Yellow Block represents MCU, the connections inside this block are internally, the connections outside are from external circuit, in the Hardware Design recommendation there is an image of the MCU, and the external components connected to this as reference. [Review your desired configuration in DCDC modes Chapter]

KW45-K32W HARDWARE DESIGN RECOMMENDATION guide

VDD_LDO_CORE has an internal connection with LDO-CORE but need an external supply configuration as the image on Design recommendations shows the value from the Source and capacitors values.

VDD_PA_2G4[VPA_2P4GHZ]is internally connected to the VDD_RF pin. VDD_RF pin gets the external source supply and with the internal connection supply VPA pin,

For more information, please refer to Table 41 2nd Note description in KW45 Datasheet and the images for DCDC configuration in HW Design Recommendations.

For the LDO_SYS configuration I would recommend referring to Table 16 LDO_SYS specifications in KW45 Datasheet.

Also, the recommended connection for unused interfaces can help you with the LDO configuration if needed. Table 62 in Datasheet.

Best Regards

Luis

Re: KW45 Power Management hardware Design

tomaru — Wed, 20 Aug 2025 01:32:06 GMT

I will continue queries about this post on other post -

KW45 VDD_RF Pin specification confirmation - NXP Community

BR,
Tomaru