S32Z/EのトピックRe: LINFlexD UART Rx FIFO sofreset

LINFlexD UART Rx FIFO sofreset

smp9 — Wed, 22 Oct 2025 17:35:09 GMT

Hello,

I'm trying to setup the LINFlexD_9 in UART Mode using TX and RX FIFO buffers. The TX FIFO works fine, but when I enable the RX FIFO to exit init mode (LINCR1[INIT] = 0) causes a soft reset.

These are the values of the registers just before setting LINCR1[INIT] to 0.

Any idea what could be happening?

Re: LINFlexD UART Rx FIFO sofreset

alejandro_e — Thu, 23 Oct 2025 02:33:10 GMT

Hello @smp9,

Thanks for contacting us again. I am assuming you are still using the S32E2. I checked how it is done in the RTD and it seems that it is needed to write both SLEEP and INIT bits at the same time:

Are you performing the your configuration in that way?

If that is not the problem, can you share a complete dump of the LLCE registers just before writing 0 to LINCR1[INIT]? address range 0x42980000 - 0x4298005C

So I can compare with an example.

Thanks

Re: LINFlexD UART Rx FIFO sofreset

smp9 — Thu, 23 Oct 2025 15:35:21 GMT

Hello @alejandro_e ,

I tried to write the SLEEP and WRITE bits at the same time, but the issue is still present.

I have attached a dump of the register values using 'Watch Registers' > 'Export' because 'Memory' > 'Export' does not work for those addresses.

Thanks.

Re: LINFlexD UART Rx FIFO sofreset

alejandro_e — Fri, 24 Oct 2025 22:04:09 GMT

Hello @smp9,

Sorry for the late reply. You can just select all the registers in the Watch registers and copy them as coma separated data. However, since there few registers for LIN you can compare them by sight with the followin:

I sopped the program here, just before going to normal mode:

With the following callstack:

And the registers were as follows:

UARTCR	0x00000027
LINSR	0x00002000
LINOCR	0x0000FFFF
UARTPTO	0x00000FFF
BDRL	0x00000000
DMARXE	0x00000000
LINTOCR	0x00000E2C
LINFBRR	0x0000000B
LINCR1	0x00000080
BDRM	0x00000000
LINESR	0x00000000
LINCR2	0x00006000
UARTCTO	0x000009FE
UARTSR	0x00000048
LINCFR	0x00000000
BIDR	0x00000000
DMATXE	0x00000000
LINTCSR	0x00000200
GCR	0x00000000
LINIER	0x00000000
LINIBRR	0x00000015

Let me know if you find any significant differences

Re: LINFlexD UART Rx FIFO sofreset

AdamH_work — Wed, 04 Feb 2026 16:08:45 GMT

Are you getting out of the boot ROM? I have run into this issue bringing up the S32E eval board. The boot ROM in the HSE processor falls into a serial boot mode if no other boot source could be booted and it accesses LINFLEX 9 to try and load a boot sequence from the UART. This behavior seems to conflict with trying to initialize the RX FIFO and causes a soft reset. Once you get out of boot ROM (by booting a valid boot source, like EMMC or QSPI) the boot ROM isn't trying to constantly access the LINFLEX 9 and enabling the RX FIFO no longer causes this soft reset.