topic S32Z RTU0 core0 performance issue in S32Z/E

S32Z RTU0 core0 performance issue

DirkEtzler — Sat, 25 Apr 2026 16:45:24 GMT

I am running some test code on S32Z270 RTU0 core 0 (R52) with RTU0_CORE_CLK set to 1GHz where the execution time seems to too long. In comparison I am running the same code on SS32K388 core 0 (CM7) with core clock set 320MHz. Given the clock frequency increase I would have expected some faster execution but instead the execution time is longer.

Build/compilation flags are held identical for both binaries (see attached txt file buildinfo.h)

(1) Since the clock configuration in the S32 Configuration Tool is kind of sophisticated for the S32Z how can I make sure the RTU0 core 0 clock frequency is 1GHz as intended?

I have routed out the RTU0_CORE_DIV2_CLK via MC_CGM_3_MUX4_CSC (e.g., SEL_CTL = 0x3D) to CLKOUT_4 (PAD_040 of BGA594) including a divider of 10 in MC_CGM_3_MUX4_DC_0 (e.g., DIV = 0x9). See also attached register readings. If I measure 50MHz at CLKOUT_4, can I presume that (a) RTU0_CORE_DIV2_CLK is 500MHz and (b) RTU0_CORE_CLK is 1GHz?

(2) I have measured the execution time of pin writes to GPIO using S32Z RTD2.0.1 and measuring high/low times of scope channel CH5 - TESTFLAG which is roughly 3.4us. Is there the possibility that you could confirm whether they seem to be alright or too slow?

(3) I am not sure what I am missing.

Re: S32Z RTU0 core0 performance issue

Joey_z — Mon, 27 Apr 2026 02:11:45 GMT

Hi，DirkEtzler

Thank you for contacting us.

1.Do you use the development board or customer board?

2. Are you using the IDE of S32DS? What is the version of IDE for you testing?

3. Could you share your testing code with me?

Joey

Re: S32Z RTU0 core0 performance issue

DirkEtzler — Mon, 27 Apr 2026 13:27:17 GMT

Hello @Joey_z,

thanks for the quick reply. Please see below my answers to the questions:

1) I am using a combination of the S32Z2XX motherboard + S32Z2XX daughterboard.
a) S32ZXX motherboard X-S32X-MB version A
b) S32ZXX daughterboard SCH-50588 REV B2 / 700-50588 REV A2

2) Code is compiled and linked using S32DS Version 3.6.7 Build 260420. There is no change when using previous releases of the S32DS such as Version 3.6.6 or 3.6.5. I am using RTD2.0.1 for S32Z2XX.

3) I will send a copy of the project using DM.

Re: S32Z RTU0 core0 performance issue

DirkEtzler — Mon, 27 Apr 2026 13:31:25 GMT

Attached is also a photo of the package markings.

Re: S32Z RTU0 core0 performance issue

Joey_z — Tue, 28 Apr 2026 11:21:34 GMT

Hi,DirkEtzler

Thank you for your reply and detail information.

I will help you to check it and reply to you late.

Joey

Re: S32Z RTU0 core0 performance issue

Joey_z — Wed, 29 Apr 2026 03:57:06 GMT

Hi,DirkEtzler

Sorry for the reply late.

(1) I have routed out the RTU0_CORE_DIV2_CLK via MC_CGM_3_MUX4_CSC (e.g., SEL_CTL = 0x3D) to CLKOUT_4 (PAD_040 of BGA594) including a divider of 10 in MC_CGM_3_MUX4_DC_0 (e.g., DIV = 0x9). See also attached register readings. If I measure 50MHz at CLKOUT_4, can I presume that (a) RTU0_CORE_DIV2_CLK is 500MHz and (b) RTU0_CORE_CLK is 1GHz?

>>>About this question, the number 7 is assigned to RTU0_CORE_DIV2_CLK, you also should program GPR3.CLKOUT4SE to set this value. Could you try to confirm if you have set this register?

Joey

Re: S32Z RTU0 core0 performance issue

DirkEtzler — Fri, 01 May 2026 13:40:20 GMT

Hello @Joey_z

With respect to this question:

>>>About this question, the number 7 is assigned to RTU0_CORE_DIV2_CLK, you also should program GPR3.CLKOUT4SE to set this value. Could you try to confirm if you have set this register?

I have checked register settings for GPR3.CLKOUT4SEL[MUXSEL] which is set to 7 to select RTU0_CORE_DIV2_CLK in the corresponding multiplexer.

Re: S32Z RTU0 core0 performance issue

DirkEtzler — Tue, 05 May 2026 12:27:03 GMT

Hello @Joey_z,

I am not sure my previous message went through and was recognized as a reply. I have checked GPR3.CLKOUT4SEL[MUXSEL] is set to 0x7 and thus, routing RTU0_CORE_DIV2_CLK through the multiplexer. Using the described configuration and seeing 50MHz at the output pin, I presume the RTU0 core is clocked with 1GHz.

If the core frequency is set to 1GHz and I still do not see the expected performance (e.g., using CoreMark testbench) what else could be incorrect configured? How can I check if the cache is configured correctly? I have been looking through the assembler startup script and also the used linker script and cannot find anything that looks suspicious.