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    <title>topic Re: Inquiry on Data Value Trace Support for S32Z27 ETM-R52 in S32Z/E</title>
    <link>https://community.nxp.com/t5/S32Z-E/Inquiry-on-Data-Value-Trace-Support-for-S32Z27-ETM-R52/m-p/2319072#M207</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIBRAA" data-complete="true" data-processed="true"&gt;The Arm Cortex-R52 implementation in the NXP S32Z27 typically does not support Data Value Trace. While the Cortex-R52 architecture itself allows for optional data trace, most automotive-grade implementations (including the S32Z series) focus on Instruction Trace and Data Address Trace to manage the extremely high bandwidth requirements of real-time cores.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_16,QJc91_17" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_15/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIBhAA" data-complete="true" data-processed="true"&gt;In the S32Z27, the Embedded Trace Macrocell (ETM) is generally limited to:&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIBxAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Instruction Trace: Tracking the program flow.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIBxAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Data Address Trace: Tracking the memory locations accessed (if configured), but not the actual data values being read or written.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_1n,QJc91_1o" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_1m/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Identification via ID Registers&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEICRAA" data-complete="true" data-processed="true"&gt;To definitively confirm the hardware capabilities of your specific silicon, you can read the ETM ID registers through your debugger.&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;Key Register: TRCIDR0&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_23,QJc91_24" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_22/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEICxAA" data-complete="true" data-processed="true"&gt;The TRCIDR0 (ID Register 0) contains bitfields that describe the supported data trace features.&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIDBAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [27:24] (DATSIZE): This field indicates the data value trace size. If this field is 0x0, data value tracing is not implemented.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDBAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [16] (TRCBB): Indicates if branch broadcast is supported.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDBAC" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [12] (COND): Indicates if conditional instruction tracing is supported.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_2n,QJc91_2o" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_2m/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;TRACE32 Diagnostic Method&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIDhAA" data-complete="true" data-processed="true"&gt;You can use the following methods in Lauterbach TRACE32 to inspect these values:&lt;/DIV&gt;
&lt;OL class="IaGLZe VimKh" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIDxAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Register Window: Use the command &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;PER.view /CoreSight&lt;/CODE&gt; and navigate to the ETM-R52 component to see a decoded view of the ID registers.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDxAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Data Dump: Execute &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;Data.dump E:&amp;lt;ETM_Base_Address&amp;gt;+0x1E0&lt;/CODE&gt; (0x1E0 is the offset for TRCIDR0) to see the raw value.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDxAC" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Command Line:&lt;/SPAN&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="QJc91_3d,QJc91_3e,QJc91_3f" data-hveid="CAEIDxAD" data-complete="true"&gt;
&lt;DIV&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-sae=""&gt;
&lt;DIV class="z0e9Qd"&gt;
&lt;DIV class="vVRw1d"&gt;t32&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr"&gt;
&lt;PRE&gt;&lt;CODE&gt;&lt;SPAN class="undefined" aria-owns="action-menu-parent-container"&gt;PRINT "ETM IDR0: " ETM.CONFIG(0) ; or appropriate register access command&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Diagnostic Errors and Confirmation&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIERAA" data-processed="true" data-complete="true"&gt;If you encounter the error "Feature not supported" when executing &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-processed="true" data-sae=""&gt;ETM.DataTrace AddressValue&lt;/CODE&gt;, it is almost certainly a hardware limitation of the S32Z27's ETM implementation.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_3v,QJc91_3w" data-complete="true" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_3u/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIEhAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Definitive Proof: If TRCIDR0.DATSIZE is 0, the hardware logic for capturing and packetizing data values is physically absent from the silicon. No software or debugger configuration can enable it.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIEhAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Alternative Diagnostics: Check the TRACE32 system settings using &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;ETM.REPository&lt;/CODE&gt;. This window often lists all detected ETM features. If "Data Value" is grayed out or marked as "None/0-bit," the feature is not present.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_49,QJc91_4a" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_48/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Summary Table for S32Z27 ETM-R52&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Fv6NCb" data-sfc-cp="" data-ved="2ahUKEwinnPaF3-CSAxUEmmoFHS8NKAEQ-q4QegYIAQgUEAA" data-complete="true" data-processed="true"&gt;
&lt;TABLE class="NRefec" data-animation-nesting="" data-sae=""&gt;
&lt;TBODY&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Feature&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_4m,QJc91_4n" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_4l/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/TH&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Typical Status in S32Z27&lt;/TH&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Register Check&lt;/TH&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Instruction Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCIDR0.PROGFLOW == 1&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Data Address Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Often Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCCONFIGR.DA&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Data Value Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Not Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCIDR0.DATSIZE == 0&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;
&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;Note: For high-speed data monitoring without ETM Data Trace, consider using the Instrumentation Trace Macrocell (ITM) for software-driven instrumentation or the LPDDR4 interface to export large trace buffers to external memory if supported by your specific board.&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;Regards&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/LI&gt;
&lt;/OL&gt;
&lt;/DIV&gt;</description>
    <pubDate>Tue, 17 Feb 2026 14:34:14 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2026-02-17T14:34:14Z</dc:date>
    <item>
      <title>Inquiry on Data Value Trace Support for S32Z27 ETM-R52</title>
      <link>https://community.nxp.com/t5/S32Z-E/Inquiry-on-Data-Value-Trace-Support-for-S32Z27-ETM-R52/m-p/2317894#M201</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We are currently setting up a real-time debugging environment using the S32Z27 processor and require clarification on its trace capabilities.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Does the &lt;STRONG&gt;ETM-R52&lt;/STRONG&gt; implementation in the &lt;STRONG&gt;S32Z27&lt;/STRONG&gt; support &lt;STRONG&gt;Data Value Trace&lt;/STRONG&gt; in addition to Instruction Trace?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;If supported, could you please point us to the specific section in the &lt;STRONG&gt;Reference Manual&lt;/STRONG&gt; or provide technical notes that describe the register configurations (e.g., &lt;STRONG&gt;TRCCONFIGR.DV&lt;/STRONG&gt;) required to enable data value tracing?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;If this feature is not implemented, could you please provide the technical confirmation, such as the fixed value of the ID register (e.g., &lt;STRONG&gt;TRCIDR0.DATSIZE&lt;/STRONG&gt;), for this specific device?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Could you provide a specific method to determine the hardware implementation status by reading ID registers, such as &lt;STRONG&gt;TRCIDR0&lt;/STRONG&gt;, using TRACE32 commands or register windows (e.g., PER window or Data.List)?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;If I encounter a &lt;STRONG&gt;"Feature not supported"&lt;/STRONG&gt; error when executing the ETM.DataTrace AddressValue command, can this be considered definitive proof of a hardware limitation of the S32Z27? Is there any other diagnostic procedure to confirm this?&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;We look forward to your detailed technical guidance.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;</description>
      <pubDate>Fri, 13 Feb 2026 14:18:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32Z-E/Inquiry-on-Data-Value-Trace-Support-for-S32Z27-ETM-R52/m-p/2317894#M201</guid>
      <dc:creator>Luke_K</dc:creator>
      <dc:date>2026-02-13T14:18:34Z</dc:date>
    </item>
    <item>
      <title>Re: Inquiry on Data Value Trace Support for S32Z27 ETM-R52</title>
      <link>https://community.nxp.com/t5/S32Z-E/Inquiry-on-Data-Value-Trace-Support-for-S32Z27-ETM-R52/m-p/2319072#M207</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIBRAA" data-complete="true" data-processed="true"&gt;The Arm Cortex-R52 implementation in the NXP S32Z27 typically does not support Data Value Trace. While the Cortex-R52 architecture itself allows for optional data trace, most automotive-grade implementations (including the S32Z series) focus on Instruction Trace and Data Address Trace to manage the extremely high bandwidth requirements of real-time cores.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_16,QJc91_17" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_15/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIBhAA" data-complete="true" data-processed="true"&gt;In the S32Z27, the Embedded Trace Macrocell (ETM) is generally limited to:&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIBxAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Instruction Trace: Tracking the program flow.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIBxAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Data Address Trace: Tracking the memory locations accessed (if configured), but not the actual data values being read or written.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_1n,QJc91_1o" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_1m/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Identification via ID Registers&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEICRAA" data-complete="true" data-processed="true"&gt;To definitively confirm the hardware capabilities of your specific silicon, you can read the ETM ID registers through your debugger.&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;Key Register: TRCIDR0&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_23,QJc91_24" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_22/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEICxAA" data-complete="true" data-processed="true"&gt;The TRCIDR0 (ID Register 0) contains bitfields that describe the supported data trace features.&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIDBAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [27:24] (DATSIZE): This field indicates the data value trace size. If this field is 0x0, data value tracing is not implemented.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDBAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [16] (TRCBB): Indicates if branch broadcast is supported.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDBAC" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Bit [12] (COND): Indicates if conditional instruction tracing is supported.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_2n,QJc91_2o" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_2m/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;TRACE32 Diagnostic Method&lt;/DIV&gt;
&lt;DIV class="AdPoic" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true" data-sae="" data-complete="true"&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIDhAA" data-complete="true" data-processed="true"&gt;You can use the following methods in Lauterbach TRACE32 to inspect these values:&lt;/DIV&gt;
&lt;OL class="IaGLZe VimKh" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIDxAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Register Window: Use the command &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;PER.view /CoreSight&lt;/CODE&gt; and navigate to the ETM-R52 component to see a decoded view of the ID registers.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDxAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Data Dump: Execute &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;Data.dump E:&amp;lt;ETM_Base_Address&amp;gt;+0x1E0&lt;/CODE&gt; (0x1E0 is the offset for TRCIDR0) to see the raw value.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIDxAC" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Command Line:&lt;/SPAN&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="QJc91_3d,QJc91_3e,QJc91_3f" data-hveid="CAEIDxAD" data-complete="true"&gt;
&lt;DIV&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-sae=""&gt;
&lt;DIV class="z0e9Qd"&gt;
&lt;DIV class="vVRw1d"&gt;t32&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr"&gt;
&lt;PRE&gt;&lt;CODE&gt;&lt;SPAN class="undefined" aria-owns="action-menu-parent-container"&gt;PRINT "ETM IDR0: " ETM.CONFIG(0) ; or appropriate register access command&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Diagnostic Errors and Confirmation&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIERAA" data-processed="true" data-complete="true"&gt;If you encounter the error "Feature not supported" when executing &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-processed="true" data-sae=""&gt;ETM.DataTrace AddressValue&lt;/CODE&gt;, it is almost certainly a hardware limitation of the S32Z27's ETM implementation.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_3v,QJc91_3w" data-complete="true" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_3u/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-complete="true" data-processed="true"&gt;
&lt;LI data-hveid="CAEIEhAA" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Definitive Proof: If TRCIDR0.DATSIZE is 0, the hardware logic for capturing and packetizing data values is physically absent from the silicon. No software or debugger configuration can enable it.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAEIEhAB" data-complete="true" data-sae=""&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-complete="true"&gt;Alternative Diagnostics: Check the TRACE32 system settings using &lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;ETM.REPository&lt;/CODE&gt;. This window often lists all detected ETM features. If "Data Value" is grayed out or marked as "None/0-bit," the feature is not present.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_49,QJc91_4a" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_48/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-complete="true" data-processed="true" data-sae=""&gt;Summary Table for S32Z27 ETM-R52&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-complete="true" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Fv6NCb" data-sfc-cp="" data-ved="2ahUKEwinnPaF3-CSAxUEmmoFHS8NKAEQ-q4QegYIAQgUEAA" data-complete="true" data-processed="true"&gt;
&lt;TABLE class="NRefec" data-animation-nesting="" data-sae=""&gt;
&lt;TBODY&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Feature&lt;SPAN class="uJ19be notranslate" data-wiz-uids="QJc91_4m,QJc91_4n" data-complete="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=QJc91_4l/TKHnVd" data-sae=""&gt;&lt;SPAN aria-hidden="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/TH&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Typical Status in S32Z27&lt;/TH&gt;
&lt;TH class="iry6k" colspan="undefined" data-sfc-cp="" data-complete="true"&gt;Register Check&lt;/TH&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Instruction Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCIDR0.PROGFLOW == 1&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Data Address Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Often Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCCONFIGR.DA&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR class="cZCYO" data-sfc-cp="" data-complete="true"&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Data Value Trace&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;Not Supported&lt;/TD&gt;
&lt;TD colspan="undefined" class="cOeeGf" data-sfc-cp="" data-complete="true"&gt;&lt;CODE class="o8j0Mc" dir="ltr" data-complete="true" data-sae=""&gt;TRCIDR0.DATSIZE == 0&lt;/CODE&gt;&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;
&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;Note: For high-speed data monitoring without ETM Data Trace, consider using the Instrumentation Trace Macrocell (ITM) for software-driven instrumentation or the LPDDR4 interface to export large trace buffers to external memory if supported by your specific board.&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEIFRAA" data-complete="true" data-processed="true" aria-owns="action-menu-parent-container"&gt;Regards&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/LI&gt;
&lt;/OL&gt;
&lt;/DIV&gt;</description>
      <pubDate>Tue, 17 Feb 2026 14:34:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32Z-E/Inquiry-on-Data-Value-Trace-Support-for-S32Z27-ETM-R52/m-p/2319072#M207</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2026-02-17T14:34:14Z</dc:date>
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