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    <title>S32KのトピックRe: LPUART receive interrupts supported?</title>
    <link>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682597#M983</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks - I found the issues and now it is working:&lt;/P&gt;&lt;P&gt;1) using LPUART 1 - vector is 33 for the LPUART1 TX/RX. &amp;nbsp;A little confused - as the LPUART0 TX/RX is actually NVIC Interrupt ID 31 (but your example uses 32).&lt;/P&gt;&lt;P&gt;2) I named my ISR routine incorrectly - it is LPUART1_1RxTx_IRQHandler (I had omitted the 'RxTx')&lt;/P&gt;&lt;P&gt;Fred&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 19 May 2017 19:43:50 GMT</pubDate>
    <dc:creator>fredericksoo</dc:creator>
    <dc:date>2017-05-19T19:43:50Z</dc:date>
    <item>
      <title>LPUART receive interrupts supported?</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682595#M981</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Reference Manual 47.4.6 says that the transmitter has two interrupts - but does not mention any receiver interrupts. &amp;nbsp;The register description for CTRL[RIE] indicates that the receive interrupt is triggered on receive buffer full. Are interrupts on receive buffer full supported? &amp;nbsp;Or is it intended to use DMA and receive interrupt that way? &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've set the NVIC ISR vector for LPUART1 receive interrupts:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;S32_NVIC-&amp;gt;&lt;SPAN class=""&gt;ICPR&lt;/SPAN&gt;[1] = 1 &amp;lt;&amp;lt; (33 % 32); &lt;SPAN class=""&gt;/* &lt;/SPAN&gt;&lt;SPAN class=""&gt;clr&lt;/SPAN&gt;&lt;SPAN class=""&gt; any pending IRQ*/&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;S32_NVIC-&amp;gt;&lt;SPAN class=""&gt;ISER&lt;/SPAN&gt;[1] = 1 &amp;lt;&amp;lt; (33 % 32); &lt;SPAN class=""&gt;/* enable IRQ */&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;S32_NVIC-&amp;gt;&lt;SPAN class=""&gt;IP&lt;/SPAN&gt;[8] =0x0A; &lt;SPAN class=""&gt;/* priority 10 */&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;and enabled&amp;nbsp;CTRL[RIE]:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;LPUART1-&amp;gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;CTRL&lt;/SPAN&gt;&lt;SPAN class=""&gt;=0x002C0000;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;/* Enable transmitter &amp;amp; receiver, no parity, 8 bit char: receive interrupts enabled*/&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and have an interrupt handler:&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;STRONG&gt;extern&lt;/STRONG&gt;&lt;/SPAN&gt; &lt;SPAN class=""&gt;"C"&lt;/SPAN&gt; &lt;SPAN class=""&gt;&lt;STRONG&gt;void&lt;/STRONG&gt;&lt;/SPAN&gt; &lt;STRONG&gt;LPUART1_IRQHandler&lt;/STRONG&gt; (&lt;SPAN class=""&gt;&lt;STRONG&gt;void&lt;/STRONG&gt;&lt;/SPAN&gt;){&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;/SPAN&gt;// UART RECEIVE&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;S32_NVIC-&amp;gt;&lt;SPAN class=""&gt;ICPR&lt;/SPAN&gt;[LPUART1_NIPR_ADDR] = 1 &amp;lt;&amp;lt; (LPUART1_IRQ % 32); &lt;SPAN class=""&gt;/* &lt;/SPAN&gt;&lt;SPAN class=""&gt;clr&lt;/SPAN&gt;&lt;SPAN class=""&gt; any pending IRQ*/&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;if&lt;/STRONG&gt;&lt;/SPAN&gt;((LPUART1-&amp;gt;&lt;SPAN class=""&gt;STAT&lt;/SPAN&gt; &amp;amp; LPUART_STAT_RDRF_MASK)&amp;gt;&amp;gt;LPUART_STAT_RDRF_SHIFT==1)&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;{&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; &lt;/SPAN&gt;&lt;SPAN class=""&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;lpuart1_receive = LPUART1-&amp;gt;&lt;SPAN class=""&gt;DATA&lt;/SPAN&gt;;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;}&lt;/P&gt;&lt;P class=""&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;but am not seeing an interrupt triggered when the receive buffer flag is full; and then it overruns.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 May 2017 21:46:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682595#M981</guid>
      <dc:creator>fredericksoo</dc:creator>
      <dc:date>2017-05-16T21:46:05Z</dc:date>
    </item>
    <item>
      <title>Re: LPUART receive interrupts supported?</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682596#M982</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;There are two interrupts in S32K144 vector table (DS, startup_S32K144.S):&lt;/P&gt;&lt;P&gt;LPUART0_RxTx_IRQHandler /*LPUART0 receive/transmit interrupt*/&lt;/P&gt;&lt;P&gt;LPUART0_ERR_IRQHandler&amp;nbsp; /*LPUART0 Receive overrun, parity error, framing error… */&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The vector numbers are 32 and 33 for LPUART0_RxTx_IRQHandler and LPUART0_ERR_IRQHandler respectively. &amp;nbsp;So you should have:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;// LPUART1 receive/transmit interrupt&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;ICPR[1] = (1 &amp;lt;&amp;lt; (32 % 32));&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;ISER[1] = (1 &amp;lt;&amp;lt; (32 % 32));&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;IP[32] = PRIORITY_N;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;// LPUART1 Receive overrun, parity error, framing error or noise error&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;ICPR[1] = (1 &amp;lt;&amp;lt; (33 % 32));&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;ISER[1] = (1 &amp;lt;&amp;lt; (33 % 32));&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;IP[33] = PRIORITY_N;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Note the IP index is also the vector number.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have tried received data via UART and the interrupt 32 is triggered when the flag is set.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 May 2017 10:51:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682596#M982</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2017-05-18T10:51:56Z</dc:date>
    </item>
    <item>
      <title>Re: LPUART receive interrupts supported?</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682597#M983</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks - I found the issues and now it is working:&lt;/P&gt;&lt;P&gt;1) using LPUART 1 - vector is 33 for the LPUART1 TX/RX. &amp;nbsp;A little confused - as the LPUART0 TX/RX is actually NVIC Interrupt ID 31 (but your example uses 32).&lt;/P&gt;&lt;P&gt;2) I named my ISR routine incorrectly - it is LPUART1_1RxTx_IRQHandler (I had omitted the 'RxTx')&lt;/P&gt;&lt;P&gt;Fred&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 19 May 2017 19:43:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-receive-interrupts-supported/m-p/682597#M983</guid>
      <dc:creator>fredericksoo</dc:creator>
      <dc:date>2017-05-19T19:43:50Z</dc:date>
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