S32K analog capability

paul_miller — Tue, 02 Feb 2021 16:43:56 GMT

I'm trying to figure out if the S32K series has an option with the analog capability to decode the following phase reversal keyed message:

The message sweeps from 203kHz to 400kHz to 100kHz and back to 203kHz over 100us. The difference between '1' and '0' states is 180deg. If I double the highest frequency, I think this means that the ADC would need to sample at least once every 1.25us.

I need to not load down the processor with this operation. I'll have some other analog sensing operations and a couple of digital communications buses. Will the S32K family support this?

Re: S32K analog capability

danielmartynek — Thu, 04 Feb 2021 10:39:09 GMT

Hello Paul,

The ADC conversion time can be calculated using the equation in the RM rev12.1, Section 44.5.4.5.

At the max. fADC = 50MHz, with sample time of just 2 ADC clock cycles in the 8-bit mode, one ADC conversion takes 0.66us.

But the sample time would be very short - this would required a very low source resistance so that the internal sample-and-hold capacitor could be charged to the input voltage.

RM rev12.1, Table 27-8. Peripheral clock summary

DS rev13, Table 40. 12-bit ADC operating conditions

S32KのトピックS32K analog capability

S32K analog capability

Re: S32K analog capability