LPIT maximum achievable frequency?

JeorgeB — Sat, 16 Jan 2021 08:44:23 GMT

Hi,

I use S32K144 and st the clock as following with using SOSC:

SOSC : 8MHz, SPLL:160MHz, CORE_CLK: 80MHz, BUS_CLK: 40MHz;

When I want to use LPIT with input clock = CLK_SRC_FIRC_DIV1 (which is 48MHz), There is not any problem and LPIT interrupt is as which I excepted. but in RM (page 567) "Maximum frequency governed by BUS_CLK" which is 40MHz!!!

48MHz is greater than 40MHz but MCU LPIT works fine !!!

Re: LPIT maximum achievable frequency?

Robin_Shen — Mon, 25 Jan 2021 06:24:53 GMT

Please check the feedback from AE team:

We need to remember that the "Bus interface clock" (BUS_CLK in this case) is the one used to feed all the logic for LPIT, in this particular example, I see that the configuration of its registers is done successfully (using the BUS_CLK), and then, the timer starts working with its functional clock (FIRCDIV2, asynchronously).

That's why apparently there is no problem. Where problems could arise is when writing/reading the LPIT regs, later in the application.

In a nutshell, they went out of the spec, but as they kept using only the functional clock, they didn't see any issues.

Best Regards,
Robin
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S32KのトピックLPIT maximum achievable frequency?

LPIT maximum achievable frequency?

Re: LPIT maximum achievable frequency?