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    <title>topic SPI clock issue in S32K</title>
    <link>https://community.nxp.com/t5/S32K/SPI-clock-issue/m-p/604979#M93</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am trying to implement the SPI module on the S32K144 RevA on a demonstration board. My program loops back MOSI on MISO, sending a number over SPI, which is incremented on reception, and sent again. When this number reaches an arbitrary high (20 000), the red LED is toggled and the number is reset (to 0). In pseudo-code:&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;myNumber = 0&lt;/P&gt;&lt;P&gt;while(1)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; send over SPI(myNumber)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; wait for reception()&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; receivedNumber = read from SPI()&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; if receivedNumber == 20000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; toggle LED&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; myNumber = 0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; else&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; increment received number&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; assign received number to myNumber&lt;/P&gt;&lt;P&gt;endif&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The LED toggling frequency should therefore be directly proportional (or at least, linked) to the SPI frequency. Here is where I cease to understand what is happening:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 16MHz and the core clock divided by DIVCORE is set to 32 MHz, the SPI bit period is roughly 250ns, causing the LED to toggle four times a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 16MHz and the core clock divided by DIVCORE is set to 16 MHz, the SPI bit period is roughly 250ns, causing the LED to toggle twice a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 32MHz and the core clock divided by DIVCORE is set to 32 MHz, the SPI bit period is roughly 125ns, causing the LED to toggle four times a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 32MHz and the core clock divided by DIVCORE is set to 16 MHz, the SPI bit period is roughly 125ns, causing the LED to toggle twice a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I do not understand why the SPI CLK/bit frequency is seemingly not linked to the LED toggling frequency. (which should be linked to the SPI transmission speed, i.e. SPI CLK frequency)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you please help me understand this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Domenico&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Oct 2016 16:00:02 GMT</pubDate>
    <dc:creator>mkdomenico</dc:creator>
    <dc:date>2016-10-26T16:00:02Z</dc:date>
    <item>
      <title>SPI clock issue</title>
      <link>https://community.nxp.com/t5/S32K/SPI-clock-issue/m-p/604979#M93</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am trying to implement the SPI module on the S32K144 RevA on a demonstration board. My program loops back MOSI on MISO, sending a number over SPI, which is incremented on reception, and sent again. When this number reaches an arbitrary high (20 000), the red LED is toggled and the number is reset (to 0). In pseudo-code:&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;myNumber = 0&lt;/P&gt;&lt;P&gt;while(1)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; send over SPI(myNumber)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; wait for reception()&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; receivedNumber = read from SPI()&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; if receivedNumber == 20000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; toggle LED&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; myNumber = 0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; else&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; increment received number&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; assign received number to myNumber&lt;/P&gt;&lt;P&gt;endif&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The LED toggling frequency should therefore be directly proportional (or at least, linked) to the SPI frequency. Here is where I cease to understand what is happening:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 16MHz and the core clock divided by DIVCORE is set to 32 MHz, the SPI bit period is roughly 250ns, causing the LED to toggle four times a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 16MHz and the core clock divided by DIVCORE is set to 16 MHz, the SPI bit period is roughly 250ns, causing the LED to toggle twice a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 32MHz and the core clock divided by DIVCORE is set to 32 MHz, the SPI bit period is roughly 125ns, causing the LED to toggle four times a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI style="text-indent: -18.0pt;"&gt;When the SPLL_DIV is set to 32MHz and the core clock divided by DIVCORE is set to 16 MHz, the SPI bit period is roughly 125ns, causing the LED to toggle twice a second.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I do not understand why the SPI CLK/bit frequency is seemingly not linked to the LED toggling frequency. (which should be linked to the SPI transmission speed, i.e. SPI CLK frequency)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you please help me understand this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Domenico&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Oct 2016 16:00:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SPI-clock-issue/m-p/604979#M93</guid>
      <dc:creator>mkdomenico</dc:creator>
      <dc:date>2016-10-26T16:00:02Z</dc:date>
    </item>
    <item>
      <title>Re: SPI clock issue</title>
      <link>https://community.nxp.com/t5/S32K/SPI-clock-issue/m-p/604980#M94</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The SPI baudrate is given by&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Baudrate = SPI functional clock / 2^TCR[PRESCALE] / (CCR[SCKDIV] +2)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The Functional clock is selected by PPC_LPSPIx register. Not sure what is your configuration in fact, but assuming the XOSC (8Mhz) is selected by PPC_LPSPIx register then using TCR[PRESCALE] =0 and CCR[SCKDIV] = 6 you get&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Baudrate = 8Mhz / 1 / 8 = 1MHz, Bit period = 1us&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then if you are using 16bit SPI frame the single SPI transmission takes 16*1us = 16us&lt;/P&gt;&lt;P&gt;In fact will be more depending complete CCR register setting.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Consired there will be no SW and HW overhead then sending of 20000 words takes 20000*16u = 320ms and the LED will toggle with this rate.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Petr&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2016 09:42:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SPI-clock-issue/m-p/604980#M94</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2016-10-27T09:42:16Z</dc:date>
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