S32K148 FTM with SPLL clock source

tomasfrcek — Tue, 08 Dec 2020 12:44:39 GMT

Hello,

I have several FTM modules with various channels and operation modes setup in my project. I use the FTM modules to generate periodic interrupts, read and generate PWM signals. So far, I only supplied the modules with SOSCDIV1_CLK (SOSC = 8MHz, DIV1 = 8MHz).

My current working setup of the FMT:

PCC_FTM2 = 0xC1000000 (PCS = 1 (SOSCDIV1_CLK), CGC = 1 (clock enabled)).
FTM2->CLKS = 3 (External clock)
FTM2->PS = 7 (divide by 128).

But now I need to generate PWM signals with very high frequency, so I need to connect SPLLDIV1_CLK instead of SOSCDIV1_CLK (SPLL_CLK = 100MHz, DIV1 = 50MHz). I setup the FTM in the following way:

PCC_FTM2 = 0xC6000000 (PCS = 6 (SPLLDIV1_CLK), CGC = 1 (clock enabled)).
FTM2->CLKS = 3 (External clock)
FTM2->PS = 7 (divide by 128).

But after configuring the clock this way, the FTM counter won't even start counting.

SPLL is also configured as system clock source. This is the SPLL configuration in SCG:

SPLLCSR = 0x03000001
SPLLDIV = 0x00000302
SPLLCFG = 0x00090000

Thanks for advice!

Tomas

Re: S32K148 FTM with SPLL clock source

tomasfrcek — Wed, 09 Dec 2020 07:49:09 GMT

Hello, again,

So I've managed to get the FTM running with the SPLLDIV1 clock sourced. The answer is in the reference manual, table 27-8. It says the maximum FTM frequency is governed by SYS_CLK. In my case, the SYS_CLK is 50MHz. Trying to supply the FTM with the same clock value 50MHz in SPLLDIV1_CLK still resulted in FTM not counting. But after dividing the SPLLDIV1_CLK down to 25MHz it finally started to work.

S32KのトピックRe: S32K148 FTM with SPLL clock source

S32K148 FTM with SPLL clock source

Re: S32K148 FTM with SPLL clock source