<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic ADC can not trigger interrupt due to PDB error in S32K</title>
    <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1191885#M9071</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am currently using module of ADC&amp;nbsp;triggering by FTM and PDB,&lt;/P&gt;&lt;P&gt;However,After a period of time, this module will trigger PDB error, which will cause the ADC interrupt to trigger abnormally, and normal sampling cannot be performed.&lt;/P&gt;&lt;P&gt;In addition,&amp;nbsp;The same problem also appears in&amp;nbsp;ADC with PDB and back-to-back triggers，The current measure is to reinitialize&lt;/P&gt;&lt;P&gt;What is the root cause of the problem and how to solve it fundamentally&lt;/P&gt;</description>
    <pubDate>Wed, 02 Dec 2020 01:31:18 GMT</pubDate>
    <dc:creator>1090097669</dc:creator>
    <dc:date>2020-12-02T01:31:18Z</dc:date>
    <item>
      <title>ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1191885#M9071</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am currently using module of ADC&amp;nbsp;triggering by FTM and PDB,&lt;/P&gt;&lt;P&gt;However,After a period of time, this module will trigger PDB error, which will cause the ADC interrupt to trigger abnormally, and normal sampling cannot be performed.&lt;/P&gt;&lt;P&gt;In addition,&amp;nbsp;The same problem also appears in&amp;nbsp;ADC with PDB and back-to-back triggers，The current measure is to reinitialize&lt;/P&gt;&lt;P&gt;What is the root cause of the problem and how to solve it fundamentally&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 01:31:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1191885#M9071</guid>
      <dc:creator>1090097669</dc:creator>
      <dc:date>2020-12-02T01:31:18Z</dc:date>
    </item>
    <item>
      <title>Re: ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1192118#M9075</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;most probably this will be due to missing or incorrect read of ADC result register.&lt;BR /&gt;Other issue could be input PDB trigger, which comes earlier than all conversions is done.&lt;/P&gt;
&lt;P&gt;Try to refer to simple S32DS "S32K144_Project_PDB" example. It configures PDB for continuous mode SW triggered, but you can test if ADC interrupt is correctly entered with configured period.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 08:04:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1192118#M9075</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2020-12-02T08:04:05Z</dc:date>
    </item>
    <item>
      <title>Re: ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1192134#M9077</link>
      <description>&lt;P&gt;hi,&lt;/P&gt;&lt;P&gt;I read all the result registers in the interrupt, and this phenomenon occurred after running for a period of time. After the PDB error is generated, I will also read all the ADC result registers, but the ADC interrupt still cannot be generated normally.&lt;BR /&gt;My configuration code is completely derived from Appendix C. Example code: ADC with PDB and back-to-back triggers in Application Note A12217.&lt;BR /&gt;My question is why the trigger period of my PDB is earlier than the conversion period? How to circumvent this problem?&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 08:13:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1192134#M9077</guid>
      <dc:creator>1090097669</dc:creator>
      <dc:date>2020-12-02T08:13:19Z</dc:date>
    </item>
    <item>
      <title>Re: ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1193181#M9106</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;are you able to share a code you have? AN12217 does not use FTM to trigger PDB.&lt;BR /&gt;Also do you use own board or some EVB?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Thu, 03 Dec 2020 11:33:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1193181#M9106</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2020-12-03T11:33:56Z</dc:date>
    </item>
    <item>
      <title>Re: ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1193564#M9119</link>
      <description>&lt;P&gt;Hello Petrs,&lt;/P&gt;&lt;P&gt;The board I use is my own hardware development board and&amp;nbsp; Following is my Code:&lt;/P&gt;&lt;P&gt;/* SW=3, ADC1 initialized to be triggered by FTM3 Init triggers */&lt;BR /&gt;void adc1_ftm_trigger_Init()&lt;BR /&gt;{&lt;BR /&gt;PCC-&amp;gt;PCCn[PCC_ADC1_INDEX] = 0; // Disable clock for ADC1&lt;BR /&gt;PCC-&amp;gt;PCCn[PCC_ADC1_INDEX] = PCC_PCCn_PCS(3) | PCC_PCCn_CGC_MASK; // Enable clock for ADC1&lt;BR /&gt;S32_NVIC-&amp;gt;ISER[ADC1_IRQn / 32] |= (1 &amp;lt;&amp;lt; (ADC1_IRQn % 32)); // Enable interrupt&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;/* Set divide ratio to 1 and select 12-bit conversion */&lt;BR /&gt;ADC1-&amp;gt;CFG1 = ADC_CFG1_ADIV(0) | ADC_CFG1_MODE(1) | ADC_CFG1_ADICLK(0);&lt;BR /&gt;/* Select hardware trigger */&lt;BR /&gt;ADC1-&amp;gt;SC2 = ADC_SC2_ADTRG_MASK;&lt;/P&gt;&lt;P&gt;/* Select channel 1 as an input and enable conversion complete interrupt */&lt;BR /&gt;//ADC1-&amp;gt;SC1[0] = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(1);&lt;BR /&gt;ADC1-&amp;gt;SC1[0] = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(0);&lt;BR /&gt;ADC1-&amp;gt;SC1[1] = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(1);&lt;BR /&gt;ADC1-&amp;gt;SC1[2] = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(2);&lt;BR /&gt;ADC1-&amp;gt;SC1[3] = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH(3);&lt;/P&gt;&lt;P&gt;INT_SYS_SetPriority(ADC1_IRQn, 1);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;/* SW=3, TRGMUX initialization to route FTM Init trigger signal into PDB0 trigger input */&lt;BR /&gt;void TRGMUX_Init()&lt;BR /&gt;{&lt;BR /&gt;//PCC-&amp;gt;PCCn[PCC_TRGMUX_INDEX] = PCC_PCCn_CGC_MASK; // Enable clock for TRGMUX module&lt;BR /&gt;TRGMUX-&amp;gt;TRGMUXn[TRGMUX_PDB1_INDEX] = TRGMUX_TRGMUXn_SEL0(0x1D); // Set FTM3 as a trigger source for PDB1&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;/* SW=3, PDB1 initialization to trigger ADC0 at the center of PWM by pre-trigger signal */&lt;BR /&gt;void pdb1_ftm_trigger_Init()&lt;BR /&gt;{&lt;BR /&gt;PCC-&amp;gt;PCCn[PCC_PDB1_INDEX] = PCC_PCCn_CGC_MASK; // Enable clock for PDB1&lt;BR /&gt;S32_NVIC-&amp;gt;ISER[PDB1_IRQn / 32] |= (1 &amp;lt;&amp;lt; (PDB1_IRQn % 32)); // Enable interrupt&lt;BR /&gt;PDB1-&amp;gt;MOD = 1000; // Set Modulo&lt;BR /&gt;PDB1-&amp;gt;CH[0].C1 = PDB_C1_TOS(1) | PDB_C1_EN(1); // Select and enable Channel0&lt;BR /&gt;PDB1-&amp;gt;CH[0].DLY[0] = 0; // Set delay&lt;BR /&gt;PDB1-&amp;gt;IDLY = 0; // Set interrupt delay&lt;BR /&gt;PDB1-&amp;gt;SC = PDB_SC_PRESCALER(0) | PDB_SC_MULT(0); // Select clock prescaler and mult factor&lt;BR /&gt;PDB1-&amp;gt;SC |= PDB_SC_TRGSEL(0) | PDB_SC_PDBIE_MASK; // Select trigger input source and enable interrupt&lt;BR /&gt;PDB1-&amp;gt;SC |= PDB_SC_PDBEIE_MASK;&lt;BR /&gt;PDB1-&amp;gt;SC |= PDB_SC_PDBEN_MASK | PDB_SC_LDOK_MASK; // Enable PDB and update PDB registers&lt;BR /&gt;}&lt;BR /&gt;/* ADC1 interrupt routine */&lt;BR /&gt;void ADC1_IRQHandler()&lt;BR /&gt;{&lt;BR /&gt;GPIO_LED2_HIGH();&lt;BR /&gt;if(adc1_trigger.adc1_trigger_mes == ADC_BY_FTM)&lt;BR /&gt;{&lt;BR /&gt;uout.val = ADC1-&amp;gt;R[0]; // Read ADC result register&lt;BR /&gt;iout.val = ADC1-&amp;gt;R[1];&lt;BR /&gt;iavg_out.val = ADC1-&amp;gt;R[2];&lt;BR /&gt;uin.val = ADC1-&amp;gt;R[3];&lt;BR /&gt;}&lt;BR /&gt;else if(adc1_trigger.adc1_trigger_mes == ADC_BY_PDB)&lt;BR /&gt;{&lt;BR /&gt;adc1_results[ADC1_CH_VOUT] = (uint16_t)ADC1-&amp;gt;R[4];&lt;BR /&gt;adc1_results[ADC1_CH_IOUT] = (uint16_t)ADC1-&amp;gt;R[5];&lt;BR /&gt;adc1_results[ADC1_CH_IAVG] = (uint16_t)ADC1-&amp;gt;R[6];&lt;BR /&gt;adc1_results[ADC1_CH_UINH] = (uint16_t)ADC1-&amp;gt;R[7];&lt;BR /&gt;uout.val = adc1_results[ADC1_CH_VOUT];&lt;BR /&gt;iout.val = adc1_results[ADC1_CH_IOUT];&lt;BR /&gt;iavg_out.val = adc1_results[ADC1_CH_IAVG];&lt;BR /&gt;uin.val = adc1_results[ADC1_CH_UINH];&lt;BR /&gt;}&lt;BR /&gt;else&lt;BR /&gt;{&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;GPIO_LED2_LOW();&lt;BR /&gt;}&lt;BR /&gt;/* PDB0 interrupt routine */&lt;BR /&gt;void PDB1_IRQHandler()&lt;BR /&gt;{&lt;BR /&gt;PDB1-&amp;gt;SC &amp;amp;= ~PDB_SC_PDBIF_MASK; // Clear PDB interrupt flag&lt;BR /&gt;if(PDB1-&amp;gt;CH[0].S &amp;amp; PDB_S_ERR_MASK)&lt;BR /&gt;{&lt;BR /&gt;PDB1-&amp;gt;CH[0].S &amp;amp;= PDB_S_ERR(0);&lt;/P&gt;&lt;P&gt;if(adc1_trigger.adc1_trigger_mes == ADC_BY_FTM)&lt;BR /&gt;{&lt;BR /&gt;uout.val = ADC1-&amp;gt;R[0]; // Read ADC result register&lt;BR /&gt;iout.val = ADC1-&amp;gt;R[1];&lt;BR /&gt;iavg_out.val = ADC1-&amp;gt;R[2];&lt;BR /&gt;uin.val = ADC1-&amp;gt;R[3];&lt;BR /&gt;}&lt;BR /&gt;else if(adc1_trigger.adc1_trigger_mes == ADC_BY_PDB)&lt;BR /&gt;{&lt;BR /&gt;adc1_results[ADC1_CH_VOUT] = (uint16_t)ADC1-&amp;gt;R[4];&lt;BR /&gt;adc1_results[ADC1_CH_IOUT] = (uint16_t)ADC1-&amp;gt;R[5];&lt;BR /&gt;adc1_results[ADC1_CH_IAVG] = (uint16_t)ADC1-&amp;gt;R[6];&lt;BR /&gt;adc1_results[ADC1_CH_UINH] = (uint16_t)ADC1-&amp;gt;R[7];&lt;BR /&gt;uout.val = adc1_results[ADC1_CH_VOUT];&lt;BR /&gt;iout.val = adc1_results[ADC1_CH_IOUT];&lt;BR /&gt;iavg_out.val = adc1_results[ADC1_CH_IAVG];&lt;BR /&gt;uin.val = adc1_results[ADC1_CH_UINH];&lt;BR /&gt;}&lt;BR /&gt;else&lt;BR /&gt;{&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;adc1_trigger.adc1_trigger_error = 1;&lt;BR /&gt;}&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;void adc_ftm_trigger_start(void)&lt;BR /&gt;{&lt;BR /&gt;TRGMUX_Init();&lt;BR /&gt;pdb1_ftm_trigger_Init();&lt;BR /&gt;adc1_ftm_trigger_Init();&lt;BR /&gt;adc1_trigger.adc1_trigger_mes = ADC_BY_FTM;&lt;BR /&gt;adc1_trigger.adc1_trigger_flag = 1;&lt;BR /&gt;adc1_trigger.adc1_trigger_error = 0;&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Fri, 04 Dec 2020 01:45:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1193564#M9119</guid>
      <dc:creator>1090097669</dc:creator>
      <dc:date>2020-12-04T01:45:26Z</dc:date>
    </item>
    <item>
      <title>Re: ADC can not trigger interrupt due to PDB error</title>
      <link>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1196498#M9186</link>
      <description>&lt;P&gt;Same question, when I use the FTM0 to trigger the PDB，&lt;SPAN&gt;ADC interrupt can&amp;nbsp; run in just once. However When I use the soft to trigger PDB , it works normally.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;void Mx_ADC_Init(void)&lt;BR /&gt;{&lt;BR /&gt;module_clk_config_t adc_clk_config={&lt;BR /&gt;.gating = 1,&lt;BR /&gt;.source = SPLL_CLK,//FIRC_CLK&lt;BR /&gt;.mul = 0,&lt;BR /&gt;.div = 0&lt;BR /&gt;};&lt;BR /&gt;const adc_converter_config_t ADC_0_ConvConfig0 = {&lt;BR /&gt;.clockDivide = ADC_CLK_DIVIDE_1,&lt;BR /&gt;.sampleTime = 80U,&lt;BR /&gt;.resolution = ADC_RESOLUTION_12BIT,&lt;BR /&gt;.inputClock = ADC_CLK_ALT_1,&lt;BR /&gt;.trigger = ADC_TRIGGER_HARDWARE,&lt;BR /&gt;.pretriggerSel = ADC_PRETRIGGER_SEL_PDB,&lt;BR /&gt;.triggerSel = ADC_TRIGGER_SEL_PDB,&lt;BR /&gt;.dmaEnable = false,&lt;BR /&gt;.voltageRef = ADC_VOLTAGEREF_VREF,&lt;BR /&gt;.continuousConvEnable = false,&lt;BR /&gt;.supplyMonitoringEnable = false&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;adc_chan_config_t ADC_0_ChnConfig0 = {&lt;BR /&gt;.interruptEnable = false,&lt;BR /&gt;.channel = ADC_INPUTCHAN_EXT2&lt;BR /&gt;};&lt;BR /&gt;adc_chan_config_t ADC_1_ChnConfig0 = {&lt;BR /&gt;.interruptEnable = false,&lt;BR /&gt;.channel = ADC_INPUTCHAN_EXT2&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pdb_adc_pretrigger_config_t pdb_1_adcTrigConfig0 = {&lt;BR /&gt;.adcPreTriggerIdx = 0U,&lt;BR /&gt;.preTriggerEnable = true,&lt;BR /&gt;.preTriggerOutputEnable = false,&lt;BR /&gt;.preTriggerBackToBackEnable = false&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;/*! @brief PDB timer configurations */&lt;BR /&gt;pdb_timer_config_t pdb_1_timerConfig0 = {&lt;BR /&gt;.loadValueMode = PDB_LOAD_VAL_IMMEDIATELY,&lt;BR /&gt;.seqErrIntEnable = false,&lt;BR /&gt;.clkPreDiv = PDB_CLK_PREDIV_BY_1,&lt;BR /&gt;.clkPreMultFactor = PDB_CLK_PREMULT_FACT_AS_1,&lt;BR /&gt;.triggerInput =PDB_TRIGGER_IN0,//PDB_SOFTWARE_TRIGGER&lt;BR /&gt;.continuousModeEnable = false,&lt;BR /&gt;.dmaEnable = false,&lt;BR /&gt;.intEnable = false,&lt;BR /&gt;.instanceBackToBackEnable = false,&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;trgmux_user_config_t trgmuxConfig;&lt;BR /&gt;trgmux_inout_mapping_config_t trgmuxInoutMappingConfig[] =&lt;BR /&gt;{&lt;BR /&gt;{TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG, TRGMUX_TARGET_MODULE_PDB0_TRG_IN, false},&lt;BR /&gt;{TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG, TRGMUX_TARGET_MODULE_PDB1_TRG_IN, false},&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;trgmuxConfig.numInOutMappingConfigs = 2;&lt;BR /&gt;trgmuxConfig.inOutMappingConfig = trgmuxInoutMappingConfig;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;CLOCK_DRV_SetModuleClock(ADC0_CLK, &amp;amp;adc_clk_config);&lt;BR /&gt;CLOCK_DRV_SetModuleClock(ADC1_CLK, &amp;amp;adc_clk_config);&lt;BR /&gt;CLOCK_DRV_SetModuleClock(PDB0_CLK, NULL);&lt;BR /&gt;CLOCK_DRV_SetModuleClock(PDB1_CLK, NULL);&lt;/P&gt;&lt;P&gt;ADC_DRV_ConfigConverter(0, &amp;amp;ADC_0_ConvConfig0);&lt;BR /&gt;ADC_DRV_ConfigConverter(1, &amp;amp;ADC_0_ConvConfig0);&lt;BR /&gt;ADC_DRV_AutoCalibration(0);&lt;BR /&gt;ADC_DRV_AutoCalibration(1);&lt;BR /&gt;ADC_0_ChnConfig0.interruptEnable = true;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 0UL, &amp;amp;ADC_0_ChnConfig0);//V current&lt;BR /&gt;ADC_0_ChnConfig0.channel = ADC_INPUTCHAN_EXT3;&lt;BR /&gt;ADC_0_ChnConfig0.interruptEnable = false;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 1UL, &amp;amp;ADC_0_ChnConfig0);&lt;BR /&gt;ADC_0_ChnConfig0.channel = ADC_INPUTCHAN_EXT4;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 2UL, &amp;amp;ADC_0_ChnConfig0);&lt;BR /&gt;ADC_0_ChnConfig0.channel = ADC_INPUTCHAN_EXT5;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 3UL, &amp;amp;ADC_0_ChnConfig0);&lt;BR /&gt;ADC_0_ChnConfig0.channel = ADC_INPUTCHAN_EXT6;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 4UL, &amp;amp;ADC_0_ChnConfig0);&lt;BR /&gt;ADC_0_ChnConfig0.channel = ADC_INPUTCHAN_EXT7;&lt;/P&gt;&lt;P&gt;ADC_0_ChnConfig0.interruptEnable = true;&lt;BR /&gt;ADC_DRV_ConfigChan(0, 5UL, &amp;amp;ADC_0_ChnConfig0);&lt;/P&gt;&lt;P&gt;ADC_DRV_ConfigChan(1, 0UL, &amp;amp;ADC_1_ChnConfig0);&lt;BR /&gt;ADC_1_ChnConfig0.channel = ADC_INPUTCHAN_EXT3;&lt;BR /&gt;ADC_DRV_ConfigChan(1, 1UL, &amp;amp;ADC_1_ChnConfig0);&lt;BR /&gt;ADC_1_ChnConfig0.channel = ADC_INPUTCHAN_EXT0;&lt;BR /&gt;ADC_DRV_ConfigChan(1, 2UL, &amp;amp;ADC_1_ChnConfig0);&lt;BR /&gt;ADC_1_ChnConfig0.channel = ADC_INPUTCHAN_EXT1;&lt;BR /&gt;ADC_DRV_ConfigChan(1, 3UL, &amp;amp;ADC_1_ChnConfig0);&lt;BR /&gt;ADC_1_ChnConfig0.channel = ADC_INPUTCHAN_EXT10;&lt;BR /&gt;ADC_DRV_ConfigChan(1, 4UL, &amp;amp;ADC_1_ChnConfig0);&lt;BR /&gt;ADC_1_ChnConfig0.channel = ADC_INPUTCHAN_EXT11;&lt;BR /&gt;ADC_DRV_ConfigChan(1, 5UL, &amp;amp;ADC_1_ChnConfig0);&lt;/P&gt;&lt;P&gt;PDB_DRV_Init(0, &amp;amp;pdb_1_timerConfig0);&lt;BR /&gt;PDB_DRV_Enable(0);&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 1;&lt;BR /&gt;pdb_1_adcTrigConfig0.preTriggerBackToBackEnable = true;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 2;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 3;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 4;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 5;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(0, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;/P&gt;&lt;P&gt;PDB_DRV_SetTimerModulusValue(0, 80*50);&lt;BR /&gt;PDB_DRV_SetAdcPreTriggerDelayValue(0, 0UL, 0UL,&lt;BR /&gt;80*1);//1us&lt;/P&gt;&lt;P&gt;PDB_DRV_LoadValuesCmd(0);&lt;/P&gt;&lt;P&gt;PDB_DRV_Init(1, &amp;amp;pdb_1_timerConfig0);&lt;BR /&gt;PDB_DRV_Enable(1);&lt;/P&gt;&lt;P&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 0;&lt;BR /&gt;pdb_1_adcTrigConfig0.preTriggerBackToBackEnable = false;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 1;&lt;BR /&gt;pdb_1_adcTrigConfig0.preTriggerBackToBackEnable = true;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 2;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 3;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 4;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;BR /&gt;pdb_1_adcTrigConfig0.adcPreTriggerIdx = 5;&lt;BR /&gt;PDB_DRV_ConfigAdcPreTrigger(1, 0UL, &amp;amp;pdb_1_adcTrigConfig0);&lt;/P&gt;&lt;P&gt;PDB_DRV_SetTimerModulusValue(1, 80*50);&lt;BR /&gt;PDB_DRV_SetAdcPreTriggerDelayValue(1, 0UL, 0UL,&lt;BR /&gt;80*1);&lt;/P&gt;&lt;P&gt;PDB_DRV_LoadValuesCmd(1);&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;TRGMUX_DRV_Init(0, &amp;amp;trgmuxConfig);&lt;/P&gt;&lt;P&gt;INT_SYS_InstallHandler(ADC0_IRQn, &amp;amp;ADC_IRQHandler, (isr_t*) 0);&lt;BR /&gt;INT_SYS_SetPriority(ADC0_IRQn,1);&lt;BR /&gt;INT_SYS_EnableIRQ(ADC0_IRQn);&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Wed, 09 Dec 2020 14:28:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-can-not-trigger-interrupt-due-to-PDB-error/m-p/1196498#M9186</guid>
      <dc:creator>lipipi</dc:creator>
      <dc:date>2020-12-09T14:28:15Z</dc:date>
    </item>
  </channel>
</rss>

