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    <title>S32KのトピックRe: How do I configure SPLL CLK?</title>
    <link>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183610#M8832</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;Robin,&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;according to Datasheert,the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;and&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;it&amp;nbsp;is&amp;nbsp;21mA,and following Code which&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;it&amp;nbsp;is&amp;nbsp;4mA,&lt;/SPAN&gt;&lt;SPAN&gt;it&amp;nbsp;should&amp;nbsp;be&amp;nbsp;less&amp;nbsp;than&amp;nbsp;1mA.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;how&amp;nbsp;to&amp;nbsp;further&amp;nbsp;reduce&amp;nbsp;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;by&amp;nbsp;the&amp;nbsp;controller?&lt;BR /&gt;&amp;nbsp;And&amp;nbsp;also&amp;nbsp;how&amp;nbsp;to&amp;nbsp;disable&amp;nbsp;the&amp;nbsp;clock&amp;nbsp;monitors?&lt;BR /&gt;And&amp;nbsp;if&amp;nbsp;possible&amp;nbsp;also&amp;nbsp;let&amp;nbsp;me&amp;nbsp;know&amp;nbsp;how&amp;nbsp;to&amp;nbsp;come&amp;nbsp;to&amp;nbsp;normal&amp;nbsp;RUN&amp;nbsp;mode&amp;nbsp;through&amp;nbsp;CAN&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Please point out my configuration errors or missing areas&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void power_cp_wakeup_set(void)/*E5*/&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;PINS_DRV_SetPinIntSel(GPIO_CP_WAKE_PORT,GPIO_CP_WAKE_PIN,PORT_INT_RISING_EDGE);&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void init_NVIC(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;power_cp_wakeup_set();&lt;/DIV&gt;&lt;DIV&gt;INT_SYS_ClearPending(PORTE_IRQn);&lt;/DIV&gt;&lt;DIV&gt;INT_SYS_SetPriority(PORTE_IRQn, 0);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;// PORTE_interrupt&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; ICPR [1] = (1 &amp;lt;&amp;lt;(63%32));&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; ISER [1] = (1 &amp;lt;&amp;lt;(63%32));&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; IP [63] = 0x10;&lt;/DIV&gt;&lt;DIV&gt;PORTE-&amp;gt; DFER |= (1 &amp;lt;&amp;lt; 5);&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void Power_RUN_to_STOP (void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;#if 0&lt;/DIV&gt;&lt;DIV&gt;/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */&lt;/DIV&gt;&lt;DIV&gt;S32_SCB-&amp;gt;SCR |= S32_SCB_SCR_SLEEPDEEP_MASK;&lt;/DIV&gt;&lt;DIV&gt;/*select stop mode*/&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMCTRL = SMC_PMCTRL_STOPM(0b00);&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;STOPCTRL = SMC_STOPCTRL_STOPO(0b01);&lt;/DIV&gt;&lt;DIV&gt;if(SMC-&amp;gt;PMSTAT == 0x01)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;asm("WFI");&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;#else&lt;/DIV&gt;&lt;DIV&gt;/* Disable the JTAG port pins */&lt;/DIV&gt;&lt;DIV&gt;/* Disable Adc Pins */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;PMC-&amp;gt;REGSC |= PMC_REGSC_BIASEN(1); // [1] CLKBIASDIS = 1 In VLPS mode, the bias current for SIRC, FIRC, PLL is disabled&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/* Disable the Fosc and Sosc from chip*/&lt;/DIV&gt;&lt;DIV&gt;SCG-&amp;gt;FIRCCSR = SCG_FIRCCSR_FIRCEN(0);&lt;/DIV&gt;&lt;DIV&gt;while(SCG-&amp;gt;FIRCCSR &amp;amp; (1 &amp;lt;&amp;lt; 24));&lt;/DIV&gt;&lt;DIV&gt;SCG-&amp;gt;SOSCCSR = SCG_SOSCCSR_SOSCEN(0);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;S32_SCB-&amp;gt;SCR |= S32_SCB_SCR_SLEEPDEEP_MASK|0x2; /* allow deep sleep mode0 */&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMPROT = SMC_PMPROT_AVLP(1); /* allow very low power mode*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMCTRL = SMC_PMCTRL_STOPM(2);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;if(SMC-&amp;gt;PMSTAT == 0x01)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;asm("WFI");&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;void&amp;nbsp;power_set_mode(POWER_SYS_TYPE&amp;nbsp;mod)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;if(mod&amp;nbsp;==&amp;nbsp;POWER_SYS_SLEEP)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;init_NVIC();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//power_can_wakeup_set();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Power_RUN_to_STOP();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Katrinal&lt;/SPAN&gt;&lt;/DIV&gt;</description>
    <pubDate>Mon, 16 Nov 2020 05:55:27 GMT</pubDate>
    <dc:creator>1090097669</dc:creator>
    <dc:date>2020-11-16T05:55:27Z</dc:date>
    <item>
      <title>How do I configure SPLL CLK?</title>
      <link>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183363#M8821</link>
      <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="未找到 spll 怎么设置.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/130033iBF18D3F6989D19C8/image-size/large?v=v2&amp;amp;px=999" role="button" title="未找到 spll 怎么设置.png" alt="未找到 spll 怎么设置.png" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 14 Nov 2020 05:04:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183363#M8821</guid>
      <dc:creator>jinsheng20</dc:creator>
      <dc:date>2020-11-14T05:04:21Z</dc:date>
    </item>
    <item>
      <title>Re: How do I configure SPLL CLK?</title>
      <link>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183607#M8831</link>
      <description>&lt;P&gt;Hi&amp;nbsp;jinsheng20,&lt;/P&gt;
&lt;P&gt;The Phase-locked loop (PLL) is not available for the S32K11x product series. That is why you cannot configure it.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Figure 27-1. Clocking diagram.png" style="width: 818px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/130110i1EC6D25DCA5EF422/image-size/large?v=v2&amp;amp;px=999" role="button" title="Figure 27-1. Clocking diagram.png" alt="Figure 27-1. Clocking diagram.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Mon, 16 Nov 2020 05:49:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183607#M8831</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2020-11-16T05:49:57Z</dc:date>
    </item>
    <item>
      <title>Re: How do I configure SPLL CLK?</title>
      <link>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183610#M8832</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;Robin,&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;SPAN&gt;according to Datasheert,the&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;and&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;it&amp;nbsp;is&amp;nbsp;21mA,and following Code which&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;it&amp;nbsp;is&amp;nbsp;4mA,&lt;/SPAN&gt;&lt;SPAN&gt;it&amp;nbsp;should&amp;nbsp;be&amp;nbsp;less&amp;nbsp;than&amp;nbsp;1mA.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;how&amp;nbsp;to&amp;nbsp;further&amp;nbsp;reduce&amp;nbsp;the&amp;nbsp;current&amp;nbsp;consumption&amp;nbsp;by&amp;nbsp;the&amp;nbsp;controller?&lt;BR /&gt;&amp;nbsp;And&amp;nbsp;also&amp;nbsp;how&amp;nbsp;to&amp;nbsp;disable&amp;nbsp;the&amp;nbsp;clock&amp;nbsp;monitors?&lt;BR /&gt;And&amp;nbsp;if&amp;nbsp;possible&amp;nbsp;also&amp;nbsp;let&amp;nbsp;me&amp;nbsp;know&amp;nbsp;how&amp;nbsp;to&amp;nbsp;come&amp;nbsp;to&amp;nbsp;normal&amp;nbsp;RUN&amp;nbsp;mode&amp;nbsp;through&amp;nbsp;CAN&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Please point out my configuration errors or missing areas&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void power_cp_wakeup_set(void)/*E5*/&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;PINS_DRV_SetPinIntSel(GPIO_CP_WAKE_PORT,GPIO_CP_WAKE_PIN,PORT_INT_RISING_EDGE);&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void init_NVIC(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;power_cp_wakeup_set();&lt;/DIV&gt;&lt;DIV&gt;INT_SYS_ClearPending(PORTE_IRQn);&lt;/DIV&gt;&lt;DIV&gt;INT_SYS_SetPriority(PORTE_IRQn, 0);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;// PORTE_interrupt&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; ICPR [1] = (1 &amp;lt;&amp;lt;(63%32));&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; ISER [1] = (1 &amp;lt;&amp;lt;(63%32));&lt;/DIV&gt;&lt;DIV&gt;S32_NVIC-&amp;gt; IP [63] = 0x10;&lt;/DIV&gt;&lt;DIV&gt;PORTE-&amp;gt; DFER |= (1 &amp;lt;&amp;lt; 5);&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;void Power_RUN_to_STOP (void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;#if 0&lt;/DIV&gt;&lt;DIV&gt;/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */&lt;/DIV&gt;&lt;DIV&gt;S32_SCB-&amp;gt;SCR |= S32_SCB_SCR_SLEEPDEEP_MASK;&lt;/DIV&gt;&lt;DIV&gt;/*select stop mode*/&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMCTRL = SMC_PMCTRL_STOPM(0b00);&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;STOPCTRL = SMC_STOPCTRL_STOPO(0b01);&lt;/DIV&gt;&lt;DIV&gt;if(SMC-&amp;gt;PMSTAT == 0x01)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;asm("WFI");&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;#else&lt;/DIV&gt;&lt;DIV&gt;/* Disable the JTAG port pins */&lt;/DIV&gt;&lt;DIV&gt;/* Disable Adc Pins */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;PMC-&amp;gt;REGSC |= PMC_REGSC_BIASEN(1); // [1] CLKBIASDIS = 1 In VLPS mode, the bias current for SIRC, FIRC, PLL is disabled&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/* Disable the Fosc and Sosc from chip*/&lt;/DIV&gt;&lt;DIV&gt;SCG-&amp;gt;FIRCCSR = SCG_FIRCCSR_FIRCEN(0);&lt;/DIV&gt;&lt;DIV&gt;while(SCG-&amp;gt;FIRCCSR &amp;amp; (1 &amp;lt;&amp;lt; 24));&lt;/DIV&gt;&lt;DIV&gt;SCG-&amp;gt;SOSCCSR = SCG_SOSCCSR_SOSCEN(0);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;S32_SCB-&amp;gt;SCR |= S32_SCB_SCR_SLEEPDEEP_MASK|0x2; /* allow deep sleep mode0 */&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMPROT = SMC_PMPROT_AVLP(1); /* allow very low power mode*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;SMC-&amp;gt;PMCTRL = SMC_PMCTRL_STOPM(2);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;if(SMC-&amp;gt;PMSTAT == 0x01)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;asm("WFI");&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;void&amp;nbsp;power_set_mode(POWER_SYS_TYPE&amp;nbsp;mod)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;if(mod&amp;nbsp;==&amp;nbsp;POWER_SYS_SLEEP)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;init_NVIC();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//power_can_wakeup_set();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Power_RUN_to_STOP();&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Katrinal&lt;/SPAN&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 16 Nov 2020 05:55:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/How-do-I-configure-SPLL-CLK/m-p/1183610#M8832</guid>
      <dc:creator>1090097669</dc:creator>
      <dc:date>2020-11-16T05:55:27Z</dc:date>
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