S32K中的主题 Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Thu, 14 May 2020 17:54:05 GMT

Can Anybody explain the usage of RxMBs (FlexCAN Mbs), FIFO and Mailboxes regading FlexCAN??
I am bit confused why we are configuring RxMb with Msg Id?? Can not we receive any message on this RxMb??

FLEXCAN_DRV_ConfigRxMb(INST_CANCOM1, RX_MAILBOX, &dataInfo, RX_MSG_ID);

Thanks in advance :smileyhappy:

Sai

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Fri, 15 May 2020 07:55:10 GMT

Hi,

please read chapters 55.5.3 Receive process and 55.5.4 Matching process of the RM to get to know whole receive/matching process.

You need to define MB's ID and mask acceptance register for the matching process; https://community.nxp.com/thread/528829

You can receive all IDs into single MB if you clear mask acceptance register, then incoming ID is don't care.

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Fri, 15 May 2020 08:47:26 GMT

Thank you @Petr Stancik for quick reply,

How can I clear mask acceptance register?? Is there any API for that ??

Best Regards,

Sai

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Fri, 15 May 2020 13:39:27 GMT

Hi,

FLEXCAN_DRV_SetRxMaskType and depending a masking type use either FLEXCAN_DRV_SetRxMbGlobalMask or

FLEXCAN_DRV_SetRxIndividualMask

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Wed, 20 May 2020 11:45:26 GMT

Hi Petr,

Thanks for info,

I am bit confusing with the filters concept with NXP micro controllers

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, 0);
FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, RX_MAILBOX, 0);

If I set the masks like above snippet

Is it going to accept only standard frames??

FLEXCAN_MSG_ID_STD is this flag decides the standard or exdended frames filtering??

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, 0);
FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, RX_MAILBOX, 0);

Is this going to receive only extended frames??

Please give one some explanation for filtering

I want set standard Id 0x08 and extended ID: 0x4bc0001 seperately? How can I set subnet mask for those IDs in FIFO mode??

Thanks in advance

Best Regards,

Saidhi reddy Sareddy

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Thu, 21 May 2020 08:36:51 GMT

Hi,

FLEXCAN_MSG_ID_STD and FLEXCAN_MSG_ID_EXT distinguish how mask will be written in the given mask acceptance register. STD mask is left shifted by 18 bits similarly as the ID set in the regular MB.

By default the IDE bit of incoming frame is checked against the bit programmed in the MB, unless CTRL2[EACEN] is set, so IDE bit can be masked too.

To receive mentioned IDs into two MBs you can use following code:

/* Set information about the data to be received */
flexcan_data_info_t dataInfo =
{
.data_length = 1U,
.msg_id_type = FLEXCAN_MSG_ID_STD,
.enable_brs = false,
.fd_enable = false,
.fd_padding = 0U
};

/* Configure RX message buffer with STD ID 0x08 */
FLEXCAN_DRV_ConfigRxMb(INST_CANCOM1, RX_MAILBOX_1, &dataInfo, 0x08);

dataInfo.msg_id_type = FLEXCAN_MSG_ID_EXT;

/* Configure RX message buffer with EXT ID 0x4bc0001 */
FLEXCAN_DRV_ConfigRxMb(INST_CANCOM1, RX_MAILBOX_2, &dataInfo, 0x4bc0001);

/* set individual masking type */
FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1, FLEXCAN_RX_MASK_INDIVIDUAL);

/* set mask affecting RX_MAILBOX_1 */
FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, RX_MAILBOX_1, 0x7FF);

/* set mask affecting RX_MAILBOX_2 */
FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, RX_MAILBOX_2, 0x1FFFFFFF);

/* Start receiving data in RX_MAILBOX_1. */
FLEXCAN_DRV_Receive(INST_CANCOM1, RX_MAILBOX_1, &recvBuff1);

/* Start receiving data in RX_MAILBOX_2 */
FLEXCAN_DRV_Receive(INST_CANCOM1, RX_MAILBOX_2, &recvBuff2);

If you want to use RXFIFO filter table must be defined too. You can refer to below example

https://community.nxp.com/docs/DOC-343091

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Fri, 22 May 2020 13:25:33 GMT

Thank you very much @Petr Stancik

You are the BEST :smileyhappy:

How can I configure the mask during in FIFO mode??
So I can not use the Id directly need to configure with Masking.

Best Regards,

Sai

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Mon, 25 May 2020 10:29:16 GMT

same IDs as before but for RXFIFO ....

/* ID Filter table, assume 8 elements are set in component inspector */
flexcan_id_table_t filterTable[8]={};
uint32_t IDlist[8] = {0x08,0x4bc0001,0x08,0x08,0x08,0x08,0x08,0x08};

uint8_t IDtype[8] = {0,1,0,0,0,0,0,0};
uint32_t IDmask[8] = {0x7FF,0x1FFFFFFF,0x7FF,0x7FF,0x7FF,0x7FF,0x7FF,0x7FF};

/* set individual masking type */
FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1, FLEXCAN_RX_MASK_INDIVIDUAL);

for(id_counter=0;id_counter<8;id_counter++)
{
filterTable[id_counter].isRemoteFrame = false;
filterTable[id_counter].isExtendedFrame = IDtype[id_counter];
filterTable[id_counter].id = IDlist[id_counter] ;

FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, IDtype[id_counter], id_counter, 0xC0000000|IDmask[id_counter]);

}
/* Configure RX FIFO ID filter table elements based on filter table defined above*/
FLEXCAN_DRV_ConfigRxFifo(INST_CANCOM1, FLEXCAN_RX_FIFO_ID_FORMAT_A, filterTable);

/* Start receiving data in RX_RXFIFO. */
FLEXCAN_DRV_RxFifo(INST_CANCOM1,&recvBuff);

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Mon, 25 May 2020 13:17:11 GMT

Hi @Petr Stancik

Thank you sooo much for your clear information regarding the setting fileters.

My requirement is only receive either standard or extended CAN frames based fileter using RxFIFO. So I did not set specific IDs in fileter.

I only set Global mask as it shows below.

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, 0);

But the Application aslo receiving the extended frames. If I will not set any Global mask application not receiving any CAN frame.

Also I tried with Extended flag

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, 0);

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, 0x10000000);

This also accepting both standard and extended flags.

Is there any way to receive any standard or extended frames using global mask with RXFIFOs.

Best Regards,

Sai

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Tue, 26 May 2020 08:42:54 GMT

Hi,

using

FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1, FLEXCAN_RX_MASK_GLOBAL);

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, 0);

the RXFIXO should accept all standard and extended messages regardless of setting id filter table.

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

saireddy_saredd — Tue, 26 May 2020 09:32:30 GMT

HI @Petr Stancik

I also got same thing in code. But, I set it FLEXCAN_MSG_ID_EXT flag but it also receives the standard frame. I did not understand exatly

Is this a bug from NXP SDK??

Because I want to make some difference between standard and extended frames?? Do I need to write extra code for fileter the extended or standard IDS?

How Can I receive only receive extended CAN frames??

How can I receive only receive standard frames??

Best Regards,

Sai

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

PetrS — Wed, 27 May 2020 11:20:44 GMT

Hi,

the Accepance mask registers are used to mask incoming ID. There is bit2bit correspondence between received ID, mask and programmed MB ID (or RXFIFO ID filter elements). The mask says if corresponding incoming ID bit is compared with programmed ID bit.

If mask bit is cleared the incoming ID bit is not compared, it is don’t care. If mask bit is set, then there must be exact match between incoming ID bit and programmed ID bit. To receive a message into a MB/RXFIFO all relevant bits with mask bit set must be equal to programmed one.

There are following rules for message filtering for different FlexCAN module configuration (assume module with 32 MBs)

a) When MCR[FEN]=0, no RX FIFO

MCR[IRMQ]=0: MB0-MB31 use RXGMASK except MB14 uses RX14MASK and MB15 used RX15MASK

MCR[IRMQ]=1: MB0-MB31 use RXIMR0-RXIMR31

b) When MCR[FEN]=1, RX FIFO used

MCR[IRMQ]=0: all RX FIFO ID elements uses RXFGMASK, rest od MBs use RXGMASK except MB14 uses RX14MASK and MB15 used RX15MASK (only if MB14/15 are not occupied by RXFIFO ID table)

MCR[IRMQ]=1: RX FIFO ID elements uses RXIMRx and RXFGMASK depending the CTRL2[RFFN] setting

So to receive message into RXFIFO you need to set the ID filter elements and mask registers.

FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1, FLEXCAN_RX_MASK_GLOBAL); // clear MCR[IRMQ] bit

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_EXT, 0); // set RXFGMASK = 0

FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, 0); // should set RXFGMASK = 0 too

FLEXCAN_MSG_ID_EXT/FLEXCAN_MSG_ID_STD just say how the 0 will be shifted

Thus as RXFGMASK = 0 neither ID bits nor IDE bit of RXFIFO ID elements are compared and so all standard and extended messages are accepted by RXFIFO.

Once reading message from RXFIFO the IDE bit of CS word shows if it was standard or extended message.

BR, Petr

Re: FlexCAN RxMbs, FIFO and MailBox concepts explanation

Sami — Fri, 23 Dec 2022 08:39:41 GMT

Hi Petrs,

I'm using S32E EVB Yeah we can able to FLEXCAN TX but we and not able to FLEXCAN Recieve Rx data.

Could you please send me the simple RX FLEXCAN/RXFIFO Recieve code,it will be great if you can help me on this.

Thanks in advance