S32KのトピックRe: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

How does FlexIO clock(sck) will be generated in 8bit-baud mode?

ravihhk2 — Sat, 18 Apr 2020 14:30:35 GMT

Hello,

I'm configuring FlexIO for SPI, Even after going through the Reference manual (S32K148) I didn't understand how the serial clock will be generated from flexio using timer in 8bit-baud mode.

In manual it is like this -

When configured for 8-bit counter mode, whenever the lower 8-bit counter decrements to
zero the timer output will toggle, the lower 8-bit counter register will reload from the
compare register and the upper 8-bit counter will decrement

if it happens like above, clock output will not be proper right(There will not be 50% Duty cycle)?

Please someone make me understand how this clock will be generated in flexio SPI??

Regards

Ravindra

Re: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

dianabatrlova — Tue, 21 Apr 2020 13:12:02 GMT

Hello,

The frequency of the transmission can be set by changing the value of the TIMCMP register

see the section "54.3.1.21 Timer Compare N Register (TIMCMP0 - TIMCMP3)"' in the RM rev 12.1

In 8-bit baud counter mode, the lower 8-bits configure the baud rate divider equal to (CMP[7:0] + 1) * 2.
The upper 8-bits configure the number of bits in each word equal to (CMP[15:8] + 1) / 2.

You can look at the doc Using FlexIO to emulate communications and timing peripherals

https://www.nxp.com/docs/en/application-note/AN12174.pdf

AN12174SW

https://www.nxp.com/webapp/Download?colCode=AN12174SW&docLang=en

Examples of the configuration can be found there.

Also, a useful explanation of FlexIO is described on this link:

Understanding FlexIO

I hope it helps.

Best regards,

Diana

Re: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

ravihhk2 — Wed, 22 Apr 2020 09:05:08 GMT

Thanks dianabatrlova‌, I understood the working of clock generation after going through https://community.nxp.com/docs/DOC-105640 link you shared.

Thanks a lot.

Regards

Ravindra

Re: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

jaikumar81 — Thu, 25 Jun 2020 15:14:49 GMT

Hi Diana Batrlova

This is related to configuring DMA for multi byte transfer and keep chip select low for the entire bytes transfer complete.

With reference to example code for Design studio, we could succesfully send the data byte by byte.

However, as per requirement we want to do multiple byte transfer say128bytes and Chip select pin be low for the entire duration.

Kindly share your suggestions or pointers to look in related to this.

Thanks in advance.

Regards,

Jayakumar

Re: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

jaikumar81 — Fri, 26 Jun 2020 05:27:14 GMT

I would like to add the configuration:

baudRate:                                   400000U,
inputClock:                                  40000000U,
driverType:                                  FLEXIO_DRIVER_TYPE_DMA,
flexio_spi_transfer_bit_order_t:   FLEXIO_SPI_TRANSFER_MSB_FIRST,
flexio_spi_transfer_size_t:          FLEXIO_SPI_TRANSFER_2BYTE,

CLK_POL: CPOL_0;
CLK_PHA: CPHA_1 ;

SCK timer config : FLEXIO_TIMER_DISABLE_TIM_CMP(3)

MasterBugffer: Size 6 bytes

masterBuffer[0] = 0x06;
masterBuffer[1] = 0x14;
masterBuffer[2] = 0xF0;
masterBuffer[3] = 0x01;
masterBuffer[4] = 0x01;
masterBuffer[5] = 0xF4;

for(cnt=0; cnt< uBufLen; ++cnt)
{
FLEXIO_SPI_DRV_MasterTransfer(&SpiflexioStateMaster, &masterBuffer[0], NULL, 2);
}

Following are the observations:

We have noticed that for 2 byte transmission(as per DMA configuration) is successful only for 2 bytes.

However, we could not notice the transmission for next consecutive remaining bytes.

Also, the way in single byte transmission we have noted DMA call back function being called is missing after updation of the DMA transfer size.

To be clear, after 2 byte transmission(as mentioned above) DMA call back function has missed thus I think further bytes are not processed for transmission.

while, when we changed to transfer_size_t: FLEXIO_SPI_TRANSFER_4BYTE,, SPI_ENABLE is not going low.

We would like to know the missing configuration, such that DMA transfer is applicable for 128 bytes with Slave select low, through out the transmission, under single transfer.

Kindly share your inputs.

Regards,

Jayakumar Appari.

Re: How does FlexIO clock(sck) will be generated in 8bit-baud mode?

jaikumar81 — Sun, 28 Jun 2020 10:06:40 GMT

The issue is resolved.

In one of the post, it has mentioned to use FlexioSPI (SPI_EN) as GPIO port to control the CS line.

Tried the same and behavior is as per expectation.