topic S32K146 SPI Master - clock irregularities in S32K

S32K146 SPI Master - clock irregularities

partis — Tue, 14 Jan 2020 14:31:26 GMT

We have a S32K146 running as an SPI master, at 4Mbps, DMA and transferring around 500 bytes per frame.

Often, at each 32nd bit multiple of data transfer, the bit is sometimes incorrect.

Looking on a 'scope, the S32K generated SPI clock, is truncated, during its high period (from 125ns to 62ns). This happens every 32 bits, consistantly. The clock appears perfect in every other respect, with no delays/stalling etc.

Is this a known issue, incorrect SPI setup (we are using AutoSar), or something else?

Re: S32K146 SPI Master - clock irregularities

namnguyenviet — Fri, 31 Jan 2020 09:00:54 GMT

Hi,

Could you please provide us your SPI configuration?

Re: S32K146 SPI Master - clock irregularities

mattiasecchiaro — Thu, 01 Sep 2022 15:06:43 GMT

Hi,

we have observed same issue on a project running on S32K148.

LPSPI2 is configured with Processor Expert as per attached image "spi_PE_setup.jpg". Furthermore:

we configure 3 wire SPI by setting PINCFG = 10b and OUTCFG = 1
we have a protocol with 9 bits words on writing and 8 bits words on reading, so at runtime we change accordingly value of FRAMESZ

As shown in image "SPI_waveform_1.jpg", first clock bit has a period that is a half of the others (so first bit is clocked at 5MHz instead of 2.5MHz). Same issue is shown in "SPI_waveform_2.jpg", where we have inserted a delay between words, to highlights that issue involves first bit of the word.

Is this a known issue? Or an incorrect SPI setup?

Thanks.