#S32K388 Enhanced RX FIFO + eDMA: Continuous Circular Buffer Reception Without CPU Interrupts

zhangyu5454 — Mon, 07 Sep 2026 09:33:02 GMT

Hi NXP Support,

I am using an S32K388 with the FlexCAN Enhanced RX FIFO and RTD. I would like to implement a continuous DMA-based CAN reception without any CPU interrupt.

My requirements are:

MCU: S32K388
CAN: Classical CAN, CAN FD disabled
CAN payload: 8 bytes
FlexCAN Enhanced RX FIFO enabled
DMA reception enabled
I need to receive CAN messages with any CAN ID, without filtering.
I want DMA to automatically transfer every received CAN frame into a RAM software ring buffer.
I do not want a FlexCAN RX interrupt.
I also do not want a DMA major-loop-complete interrupt.
DMA should continue running automatically without the CPU having to call FlexCAN_Ip_RxFifo() again.
Ideally, each received FIFO element should trigger a DMA transfer immediately, so I do not want to wait for a large FIFO watermark.

I checked the RTD source code. In FlexCAN_StartRxMessageEnhancedFifoData(), I found that the driver configures DMA approximately as follows:

Source address              = Enhanced RX FIFO output
Source transfer size        = 4 bytes
Source offset               = 4 bytes
Destination transfer size   = 4 bytes
Destination offset          = 4 bytes
Minor loop size             = 80 bytes
Major loop count            = num_enhanced_watermark
EnMajorInt                  = TRUE
DisAutoHwRequest            = TRUE

I understand that the current RTD implementation performs a finite DMA transfer and then stops, requiring FlexCAN_Ip_RxFifo() to be called again.

My question is:

Is it possible on S32K388 to configure the eDMA TCD so that the FlexCAN Enhanced RX FIFO DMA request continuously transfers received FIFO elements into a circular RAM buffer, without any CPU interrupt or software re-arming?

In particular, can Destination Modulo and/or another eDMA TCD feature be used to implement this continuous ring buffer?

If this is possible, could you please provide an example configuration or point me to an NXP example/reference implementation?

I am willing to modify the RTD FlexCAN driver or configure the eDMA TCD directly if necessary.

Thanks!

Re: #S32K388 Enhanced RX FIFO + eDMA: Continuous Circular Buffer Reception Without CPU Interrupts

Julián_AragónM — Tue, 08 Sep 2026 23:33:07 GMT

Hello @zhangyu5454,

The driver is written in a way that requires FlexCAN_Ip_RxFifo() to be called in order to re-arm reception inside the FLEXCAN_EVENT_DMA_COMPLETE event.

It should be possible to have a continuous transfer from DMA to buffer; however, you will need to modify the RTDs or create your own driver. Unfortunately, this is out of our support scope, and if done, verification and functionality should be tested by you.

You would have to set TCDn_CSR[D_REQ] = 0 (DisAutoHwRequest = FALSE) & TCDn_CSR[INTMAJOR] in order to keep the channel armed and disable interrupts, as well as configure your circular data queue. You can refer to S32K3's DMA Training Presentation, under S32K3 Product Page and 'Secure Files'.

Best regards,
Julián

S32Kのトピック#S32K388 Enhanced RX FIFO + eDMA: Continuous Circular Buffer Reception Without CPU Interrupts

#S32K388 Enhanced RX FIFO + eDMA: Continuous Circular Buffer Reception Without CPU Interrupts

Re: #S32K388 Enhanced RX FIFO + eDMA: Continuous Circular Buffer Reception Without CPU Interrupts