Can I use the same IRQ for multi core

Licunhao — Mon, 10 Aug 2026 09:54:22 GMT

Hi helper

I am using S32K358 multi core.

Using Eirq for io interrupt.

I have a question:

I want core0 use eirq0 and core2 use eirq1

But the two irq channel trigger the same IRQ handler SIUL2_EXT_IRQ_0_7_ISR

So there is the problem. If eirq0 and eirq1 both come. The Both core trigger

SIUL2_EXT_IRQ_0_7_ISR. Both core operate the same register.

It will be cause bad software expectation.It will clear other non-init channel.

Do I understand OK?

please give me a help.

Brs

Re: Can I use the same IRQ for multi core

PavelL — Mon, 10 Aug 2026 12:22:52 GMT

Hello @Licunhao ,

Your understanding is partially correct.

On S32K3 devices, the SIUL2 external interrupt inputs are grouped into interrupt vectors. Therefore, EIRQ0 and EIRQ1 belong to the same interrupt group and are handled by the same grouped interrupt handler, for example SIUL2_EXT_IRQ_0_7_ISR.

So, EIRQ0 and EIRQ1 cannot be used as two fully independent interrupt vectors.

If the same SIUL2 interrupt group is routed or enabled on more than one core, both cores may enter the same interrupt handler and access the same SIUL2 registers. This can lead to unexpected behavior if the software does not implement proper multicore synchronization and ownership of the SIUL2 interrupt group.

However, the SIUL2 interrupt flags are still available per individual EIRQ channel. A correct interrupt handler should check which EIRQ flag is pending and clear only the corresponding flag bit. The status flags should not be cleared globally or with an incorrect mask, otherwise another pending EIRQ flag could be affected.

For a multicore application, I would recommend one of these approaches:

Assign the whole SIUL2 interrupt group, for example EIRQ0 to EIRQ7, to one core only. This core should handle the grouped ISR and, if needed, notify another core by software or inter-core communication.
If you need independent interrupt routing to different cores, use EIRQ channels from different SIUL2 interrupt groups, for example one channel from EIRQ0 to EIRQ7 and another channel from EIRQ8 to EIRQ15, if this is possible with your pin configuration.
If both cores must access the same SIUL2 registers, the access must be protected by a proper multicore synchronization mechanism. But in general, a single-owner model for the SIUL2 interrupt group is cleaner and safer.

Best regards,

Pavel

topic Can I use the same IRQ for multi core in S32K

Can I use the same IRQ for multi core

Re: Can I use the same IRQ for multi core