https://community.nxp.com/t5/S32K/GPIO/m-p/2402779#M60306 <P>Hi</P> <P>Please refer to previous similar discussions: <A href="https://community.nxp.com/t5/S32K/S32K3-GPIO-HIGH-Z/td-p/2008049" target="_self">S32K3 GPIO HIGH-Z</A></P> <P>If the pin may have previously enabled internal pull, in order to satisfy the tristate definition in S32K3XXRM, <SPAN>Siul2_Port_Ip_SetPullSel</SPAN>(..., PORT_INTERNAL_PULL_NOT_ENABLED) should be called to ensure PUE=0;</P> <P>Best Regards,<BR />Robin</P> Fri, 07 Aug 2026 08:33:01 GMT Robin_Shen 2026-08-07T08:33:01Z https://community.nxp.com/t5/S32K/GPIO/m-p/2402727#M60295 <P>Based on the S32K324 MCU, how to configure a GPIO to high‑impedance state using S32DS.</P> Fri, 07 Aug 2026 05:26:42 GMT https://community.nxp.com/t5/S32K/GPIO/m-p/2402727#M60295 代码织梦师 2026-08-07T05:26:42Z https://community.nxp.com/t5/S32K/GPIO/m-p/2402779#M60306 <P>Hi</P> <P>Please refer to previous similar discussions: <A href="https://community.nxp.com/t5/S32K/S32K3-GPIO-HIGH-Z/td-p/2008049" target="_self">S32K3 GPIO HIGH-Z</A></P> <P>If the pin may have previously enabled internal pull, in order to satisfy the tristate definition in S32K3XXRM, <SPAN>Siul2_Port_Ip_SetPullSel</SPAN>(..., PORT_INTERNAL_PULL_NOT_ENABLED) should be called to ensure PUE=0;</P> <P>Best Regards,<BR />Robin</P> Fri, 07 Aug 2026 08:33:01 GMT https://community.nxp.com/t5/S32K/GPIO/m-p/2402779#M60306 Robin_Shen 2026-08-07T08:33:01Z