<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックRe: s32k344, LPSPI small clock gap between frames of a continuous sequence</title>
    <link>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2398934#M60057</link>
    <description>&lt;P&gt;The data for MOSI and MISO is empty. Do you have right SPI bus hardware schematics design?&lt;/P&gt;</description>
    <pubDate>Sat, 25 Jul 2026 15:05:02 GMT</pubDate>
    <dc:creator>db16122</dc:creator>
    <dc:date>2026-07-25T15:05:02Z</dc:date>
    <item>
      <title>s32k344, LPSPI small clock gap between frames of a continuous sequence</title>
      <link>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2398853#M60053</link>
      <description>&lt;P&gt;- I am having a problem communicating between an NXP MCU S32K344 LPSPI module (Controller) and a Holt HI-35930 (Peripheral).&lt;/P&gt;&lt;P&gt;The code is writing 2 frames, each an 8 bit word. over the LPSPI to an ARINC communication device HI-35930.&amp;nbsp; I verified all settings are correct. cpol = 0, cpha = 0,&amp;nbsp; LSBF = MSB, BYSW=no, RXMSK, TXMSK =0, TCR[FRMSZ]=7.&lt;/P&gt;&lt;P&gt;The code uses the TRC[CONT and TRC[CONTC] bits to control the PCS. The PCS stays asserted for the entire sequence of 2 frames, see picture. The clock, likewise pulses over the 2 frames. The SOUT signal has the expected data on it, frame 1 = opcode 0x80, frame 2 - dummy data 0x00&lt;/P&gt;&lt;P&gt;The problem is with SIN. There is no data back. ( opcode 0x80 is to read a register where I was expecting at least one bit set high).&lt;/P&gt;&lt;P&gt;The RXCOUNT does increment on each frame to a max of 2.&lt;/P&gt;&lt;P&gt;-Using the same settings, I concatenate the same opcode and data into one 16-bit frame, set TRC[CONT and TRC[CONTC] = 0 since there is one frame TRC[FRMSZ]=15. The transmission works and SIN returns real data.&lt;/P&gt;&lt;P&gt;What do you think is wrong here?&lt;/P&gt;&lt;P&gt;Yellow - PCS signal&lt;/P&gt;&lt;P&gt;Pink - Clock signal&lt;/P&gt;&lt;P&gt;Blue - SIN to the MCU&lt;/P&gt;&lt;P&gt;Green - SOUT from the MCU&lt;/P&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Jul 2026 20:30:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2398853#M60053</guid>
      <dc:creator>ekmas-19</dc:creator>
      <dc:date>2026-07-24T20:30:59Z</dc:date>
    </item>
    <item>
      <title>Re: s32k344, LPSPI small clock gap between frames of a continuous sequence</title>
      <link>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2398934#M60057</link>
      <description>&lt;P&gt;The data for MOSI and MISO is empty. Do you have right SPI bus hardware schematics design?&lt;/P&gt;</description>
      <pubDate>Sat, 25 Jul 2026 15:05:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2398934#M60057</guid>
      <dc:creator>db16122</dc:creator>
      <dc:date>2026-07-25T15:05:02Z</dc:date>
    </item>
    <item>
      <title>Re: s32k344, LPSPI small clock gap between frames of a continuous sequence</title>
      <link>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2399118#M60070</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/252673"&gt;@ekmas-19&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;You described the transmission as sending 2 bytes — 0x80 and 0x00. However, the oscilloscope clearly shows 2 x 32-bit words separated by a small gap, not 2 x 8-bit frames. Can you clarify this?&lt;/P&gt;
&lt;P&gt;Regarding the inter-frame gap — this is expected behaviour. CONT = 1 only keeps CS/PCS asserted between frames; it does not affect SCK. The clock behaves exactly as it would with CONT = 0.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 27 Jul 2026 08:35:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k344-LPSPI-small-clock-gap-between-frames-of-a-continuous/m-p/2399118#M60070</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-07-27T08:35:07Z</dc:date>
    </item>
  </channel>
</rss>

