S32KのトピックRe: S32K comparator tolerance/offset

S32K comparator tolerance/offset

Sid_Zhou — Thu, 16 Jul 2026 09:30:54 GMT

we are having some test on the comparator of S32K116:
we apply an input voltage(238mV) to INN (or INP), use bandgap as reference, then we increase VOSEL from 0 to 255 and monitor when the comparator output changed.

Somehow, we see different tolerance/offset on MCU2 when the connection of input voltage and bandgap is swapped. (Details shown in Test1 and Test2)

1) Is this some kind of known feature like VAIO or something else?
2) For this tolerance/offset, is it stable and can we eliminate this by calibration?
(like record the trigger VOSEL at the target voltage)

Test1: Input Voltage on V-, Bandgap on V+, Low Speed Mode

Test2: Input Voltage on V+, Bandgap on V-, Low Speed Mode

Re: S32K comparator tolerance/offset

Robin_Shen — Fri, 17 Jul 2026 03:38:42 GMT

Hi Sid_Zhou,

Which CMP0_IN pin are you connecting the input voltage to?

When swapping INN and INP, is the input voltage still being input through the same CMP0_IN pin?

Also, the BandGap voltage range is between 0.97-1.03V. Have you considered temporarily ruling out issues caused by different BandGap voltages on the two MCUs? For example, could you use a different CMP0_IN pin to input a more accurate external voltage reference?

Have you checked whether the VDD/VDDA voltages of the two S32K1s are the same?

Were OFFSET=1 and HYSTCTR=0 confirmed during debugging?

I noticed you increased the input voltage and recorded VOSEL. Have you tested decreasing the input voltage and recording VOSEL? Also, check if the Analog comparator hysteresis is affected, although I see you configured HYSTCTR=0.

Take two S32K116 photos and tell me the MCU mask.

Best Regards,
Robin

Re: S32K comparator tolerance/offset

Sid_Zhou — Fri, 17 Jul 2026 07:56:04 GMT

1) Input Pin
CMP0_IN is always set to channel 0. (PIN26, PTA0)
Yes, input voltage still being input through the same CMP0_IN Pin26, PTA0.
2) Bandgap
The feature I want to figure out is not the difference between two MCU. It is this different tolerance/offset from the same MCU when INN and INP is swapped. I think the bandgap should not change during this swapped. (The data of MCU1 here is just use as reference)
3) VDD/VDDA:
The two MCU are using same +3.3V network (LDO within 1.25% tolerance).
I am fully understanding there will be difference between MCUs bandgap, but, again, it is the difference during swapped I am checking.
4) test method
The test data above is not increasing input voltage, it is using fixed input voltage, and increasing VOSEL. (For decreasing VOSEL, i have not test yet, will check this later.)
As for increasing/decreasing input voltage with fixed VOSEL, there is similar -9mV.

5) Hysteresis
I do have test data for hysteresis in low-speed mode:
Test data here is fixing input voltage and increase VOSEL:

6) MCU photos
you can refer to attached photo "MCU1.PNG" and "MCU2.PNG"
Solder mask is
FS32K11-6LFMFM-ON96V-S12YM16