S32KのトピックRe: High Drive Strength on S32K3

High Drive Strength on S32K3

kscz — Fri, 19 Jun 2026 21:09:31 GMT

The S32K3XX reference manual talks about the "drive-strength enable" bits, but doesn't appear to define what this means - the closest reference I can find is that it seems correlated with maximum frequency supported by certain pins (page 42 of the S32K3XXRM/Section 4.4.1)

Is there something explicit in terms of maximum current draw or other things I should be aware of for why I should or should not enable "drive-strength"?

Re: High Drive Strength on S32K3

db16122 — Sat, 20 Jun 2026 04:02:44 GMT

GPIO-Standard: Switching up to 10 MHz High drive-strength not supported. Slew-rate control not supported.
—
GPIO-Standard plus: Switching up to 25 MHz Supports high drive-strength. Slew-rate control not supported.
—
GPIO-Medium: Switching up to 50 MHz Supports high drive-strength. Supports slew-rate control.
—
GPIO-Fast: Switching up to 120 MHz Supports high drive-strength. Supports slew-rate control.

Re: High Drive Strength on S32K3

kscz — Sat, 20 Jun 2026 21:42:01 GMT

Yes, that is exactly the text of the section I cited in my question. That doesn't tell me why I should or shouldn't enable "drive strength" - it just tells me that some pins support it, and that some switching rates are related to it.

If I were driving an LED with it, would it be capable of sinking more current? How much more current?

Is it purely a slew-rate change?

Is there a reason not to enable it, if the pin supports it? Will my chip dissipate more heat if I enable it?

Re: High Drive Strength on S32K3

db16122 — Sun, 21 Jun 2026 01:13:32 GMT

Hardware Design Guidelines for S32K39x, S32K37x and S32K36x Microcontrollers

Re: High Drive Strength on S32K3

Robin_Shen — Mon, 22 Jun 2026 00:59:23 GMT

The S32K3XX Reference Manual (S32K3XXRM) states that the Pad Type "GPIO-Standard" does not support high drive strength, whereas "GPIO-Standard Plus", "GPIO-Medium", and "GPIO-Fast" support high drive strength.

For GPIO Pad Type, please refer to the S32K344_IO Signal Table, specifically column H, in the Excel attachment S32K344_S32K324_S32K314_IOMUX.xlsx provided with the S32K3XXRM.

Best Regards,
Robin
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Re: High Drive Strength on S32K3

kscz — Mon, 06 Jul 2026 21:03:50 GMT

As I told the previous poster, I know which pins do and do not support "high drive strength," that is not the issue!

But fortunately, in the background you had the relevant chunk of information: in S32K3xx.pdf, Table 27. GPIO DC electrical specifications, appears to have what I need.

It looks like it doubles the output current of the pins to enable the "DSE = 0" vs "DSE = 1"