S32K388 Hardware Specs Verification — RAM/ROM/Cache Sizes, Bus Connections, Power, NVIC & Watchdog

xlele — Fri, 05 Jun 2026 05:45:04 GMT

I am documenting the S32K388 hardware architecture for our project and have compiled the specifications below based on the Reference Manual (RM). However, I have uncertainties that I need to verify with the community. I would appreciate confirmation or pointers to the exact RM chapters.

Re: S32K388 Hardware Specs Verification — RAM/ROM/Cache Sizes, Bus Connections, Power, NVIC & Wa

davidtosenovjan — Fri, 05 Jun 2026 15:37:49 GMT

The provided table is mostly correct in terms of memory sizes (8 MB PFLASH, 128 KB DFLASH, ~1.125 MB SRAM including ~384 KB TCM, and 16 KB I/D cache per core).

However, some points need clarification:

- Flash does not operate at a fixed “250 MHz”. Its performance depends on wait states and controller configuration, not a simple frequency.
- Access to Flash and SRAM is through the system interconnect (AXBS crossbar), while TCM is directly connected to the core and runs at core frequency.
- The “64-bit XBAR” description is an oversimplification; the architecture uses a multi-layer crossbar with multiple masters and ports.
- The stated 12-cycle interrupt latency corresponds to the theoretical Cortex-M7 minimum. Actual latency is higher depending on system conditions.
- There is no EWM module on S32K3 devices; the primary watchdog is SWT.

For performance analysis, it is important to distinguish between TCM (deterministic, core-coupled), SRAM (via interconnect), and Flash (via controller with latency).

topic S32K388 Hardware Specs Verification — RAM/ROM/Cache Sizes, Bus Connections, Power, NVIC & Watchdog in S32K

S32K388 Hardware Specs Verification — RAM/ROM/Cache Sizes, Bus Connections, Power, NVIC & Watchdog

Re: S32K388 Hardware Specs Verification — RAM/ROM/Cache Sizes, Bus Connections, Power, NVIC & Wa