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  <channel>
    <title>S32KのトピックRe: S32K312 CAN MB vs RxFIFO</title>
    <link>https://community.nxp.com/t5/S32K/S32K312-CAN-MB-vs-RxFIFO/m-p/2374746#M58967</link>
    <description>&lt;P&gt;Hi@&lt;A id="link_6" class="lia-link-navigation lia-page-link lia-user-name-link" href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200168" aria-label="View Profile of lua40927" target="_blank"&gt;&lt;SPAN class=""&gt;lua40927&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;1.&lt;SPAN&gt;Yes — if you configure multiple RX message buffers with the same acceptance criteria, FlexCAN does&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;simply overwrite MB0 immediately. With the normal matching behavior, it scans RX MBs from low number to high number, and if the first matching MB is not “free-to-receive,” it keeps looking for another matching MB that is free. So if MB0 already contains an unread matching frame, the next matching frame can be stored in MB1, then MB2, and so on, as long as those MBs are also matching and free. If no matching/free MB remains, FlexCAN overwrites the&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;last matched MB&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;and sets its CODE to&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;OVERRUN&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;2.No such info available.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I can give you some experience summaries and comparisons.&lt;/SPAN&gt;&lt;/P&gt;
&lt;UL class=""&gt;
&lt;LI class=""&gt;If your priority is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;strict receive order + simpler draining logic&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, FIFO is better aligned to that use case because it is a true ordered queue with internal pointer handling.,&lt;/LI&gt;
&lt;LI class=""&gt;If your priority is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;maximum buffering depth using many RX slots&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for Classic CAN traffic, dedicating many MBs to reception can give you much more room than the six-deep legacy FIFO, at the cost of more software management and possible reordering by timestamp.,,&lt;/LI&gt;
&lt;LI class=""&gt;If you want&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;DMA-based reception&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, the available S32K material says DMA is supported for RX FIFO, not MBs. Specifically, an S32K support answer states “DMA is supported only over RXFIFOs (legacy or enhanced) no over MBs.”&lt;/LI&gt;
&lt;LI class=""&gt;On S32K312, &lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;Enhanced Rx FIFO is available only on FlexCAN0&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and that legacy and enhanced FIFO cannot be enabled at the same time.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Note:&lt;BR /&gt;We recommend using your company email to register your NXP account, as general email addresses offer limited technical support.&lt;/P&gt;</description>
    <pubDate>Tue, 02 Jun 2026 03:35:08 GMT</pubDate>
    <dc:creator>Senlent</dc:creator>
    <dc:date>2026-06-02T03:35:08Z</dc:date>
    <item>
      <title>S32K312 CAN MB vs RxFIFO</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-CAN-MB-vs-RxFIFO/m-p/2374676#M58962</link>
      <description>&lt;P class=""&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN&gt;I would like to ask a few questions regarding the CAN reception mechanism on the S32K312, specifically the differences between Message Buffers (MBs) and Rx FIFO.&lt;/SPAN&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;SPAN&gt;If I configure MB0 to MB30 as receive message buffers and set them to accept all CAN messages, what happens when a new message arrives while MB0 already contains an unread message? Will the new message be automatically stored in MB1 (or the next available MB), or will it overwrite MB0 / be discarded?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Is there any performance difference between using Message Buffers (MBs) and Rx FIFO for CAN reception? For example, is one method faster than the other in terms of receiving back-to-back CAN frames, or is the difference negligible?&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P class=""&gt;&lt;SPAN&gt;I am trying to determine which approach is more suitable for handling a high volume of CAN traffic on the S32K312.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you for your help.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 02 Jun 2026 01:42:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-CAN-MB-vs-RxFIFO/m-p/2374676#M58962</guid>
      <dc:creator>lua40927</dc:creator>
      <dc:date>2026-06-02T01:42:41Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 CAN MB vs RxFIFO</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-CAN-MB-vs-RxFIFO/m-p/2374746#M58967</link>
      <description>&lt;P&gt;Hi@&lt;A id="link_6" class="lia-link-navigation lia-page-link lia-user-name-link" href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200168" aria-label="View Profile of lua40927" target="_blank"&gt;&lt;SPAN class=""&gt;lua40927&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;1.&lt;SPAN&gt;Yes — if you configure multiple RX message buffers with the same acceptance criteria, FlexCAN does&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;simply overwrite MB0 immediately. With the normal matching behavior, it scans RX MBs from low number to high number, and if the first matching MB is not “free-to-receive,” it keeps looking for another matching MB that is free. So if MB0 already contains an unread matching frame, the next matching frame can be stored in MB1, then MB2, and so on, as long as those MBs are also matching and free. If no matching/free MB remains, FlexCAN overwrites the&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;last matched MB&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;and sets its CODE to&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;OVERRUN&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;2.No such info available.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I can give you some experience summaries and comparisons.&lt;/SPAN&gt;&lt;/P&gt;
&lt;UL class=""&gt;
&lt;LI class=""&gt;If your priority is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;strict receive order + simpler draining logic&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, FIFO is better aligned to that use case because it is a true ordered queue with internal pointer handling.,&lt;/LI&gt;
&lt;LI class=""&gt;If your priority is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;maximum buffering depth using many RX slots&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for Classic CAN traffic, dedicating many MBs to reception can give you much more room than the six-deep legacy FIFO, at the cost of more software management and possible reordering by timestamp.,,&lt;/LI&gt;
&lt;LI class=""&gt;If you want&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;DMA-based reception&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, the available S32K material says DMA is supported for RX FIFO, not MBs. Specifically, an S32K support answer states “DMA is supported only over RXFIFOs (legacy or enhanced) no over MBs.”&lt;/LI&gt;
&lt;LI class=""&gt;On S32K312, &lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;Enhanced Rx FIFO is available only on FlexCAN0&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and that legacy and enhanced FIFO cannot be enabled at the same time.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Note:&lt;BR /&gt;We recommend using your company email to register your NXP account, as general email addresses offer limited technical support.&lt;/P&gt;</description>
      <pubDate>Tue, 02 Jun 2026 03:35:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-CAN-MB-vs-RxFIFO/m-p/2374746#M58967</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2026-06-02T03:35:08Z</dc:date>
    </item>
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