https://community.nxp.com/t5/S32K/emac-mii-rmii-tx-clock-question/m-p/2368520#M58745 <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="cszhang_0-1779286186364.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/386196i1B99A3458BE45EB3/image-size/medium?v=v2&amp;px=400" role="button" title="cszhang_0-1779286186364.png" alt="cszhang_0-1779286186364.png" /></span></P><P>the screen shot is from&nbsp;lwip_baremetal_s32k344.mex, is the&nbsp;emac_mii_rmii_tx&nbsp; from the switch MII_TX_CLK?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="cszhang_1-1779286347847.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/386197i0824CAC7152EA87D/image-size/medium?v=v2&amp;px=400" role="button" title="cszhang_1-1779286347847.png" alt="cszhang_1-1779286347847.png" /></span></P><P>&nbsp;</P><P>&nbsp;</P> Wed, 20 May 2026 14:13:13 GMT cszhang 2026-05-20T14:13:13Z https://community.nxp.com/t5/S32K/emac-mii-rmii-tx-clock-question/m-p/2368520#M58745 <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="cszhang_0-1779286186364.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/386196i1B99A3458BE45EB3/image-size/medium?v=v2&amp;px=400" role="button" title="cszhang_0-1779286186364.png" alt="cszhang_0-1779286186364.png" /></span></P><P>the screen shot is from&nbsp;lwip_baremetal_s32k344.mex, is the&nbsp;emac_mii_rmii_tx&nbsp; from the switch MII_TX_CLK?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="cszhang_1-1779286347847.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/386197i0824CAC7152EA87D/image-size/medium?v=v2&amp;px=400" role="button" title="cszhang_1-1779286347847.png" alt="cszhang_1-1779286347847.png" /></span></P><P>&nbsp;</P><P>&nbsp;</P> Wed, 20 May 2026 14:13:13 GMT https://community.nxp.com/t5/S32K/emac-mii-rmii-tx-clock-question/m-p/2368520#M58745 cszhang 2026-05-20T14:13:13Z https://community.nxp.com/t5/S32K/emac-mii-rmii-tx-clock-question/m-p/2369140#M58761 <P>Hi,</P> <P>lwip_baremetal_s32k344 example configure xMII interface for RMII mode so emac_mii_rmii_tx is input and is expecting 50MHz reference clock (that's why there is a /2 divider).</P> <P>On switch, like SJA1110,&nbsp;RMII REF_CLK functionality is available on pins MIIx_RX_CLK or MIIx_TX_CLK and can be software selected for flexibility.</P> <P>BR, Petr</P> <P>&nbsp;</P> <P>&nbsp;</P> Thu, 21 May 2026 05:42:15 GMT https://community.nxp.com/t5/S32K/emac-mii-rmii-tx-clock-question/m-p/2369140#M58761 PetrS 2026-05-21T05:42:15Z