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    <title>topic Re: S32K394: Clarification on STCU2 self-test and system RAM retention across functional reset in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361506#M58405</link>
    <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Many thanks for your response.&lt;/P&gt;&lt;P&gt;Our project uses the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;region to exchange information between three different software images:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Boot Manager&lt;/STRONG&gt;,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Bootloader&lt;/STRONG&gt;, and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Application&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Only after a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Power-on Reset / Destructive Reset,&lt;/STRONG&gt;&amp;nbsp;the Boot Manager initialize this Standby SRAM region.&lt;/P&gt;&lt;P&gt;After a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;, this memory region is intentionally left untouched so that it can retain useful information for the other software images.&lt;/P&gt;&lt;P&gt;The current issue for us is that after&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;BIST self-test&lt;/STRONG&gt;, the SRAM contents appear to be invalidated, even though the resulting reset is a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;As a result, when the Boot Manager later reads a value from&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM&lt;/STRONG&gt;, it triggers an exception.&lt;/P&gt;&lt;P&gt;Our assumption, based on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Section 29.2.2 "Chip reset types"&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K396RM Rev. 4, 11/2024&lt;/STRONG&gt;, is that&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;loss of SRAM contents should be associated with destructive reset&lt;/STRONG&gt;, not functional reset.&lt;/P&gt;&lt;P&gt;Therefore, we would like to understand the following:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there a specific reason why&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;BIST self-test&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;results in a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;, even though it appears to cause&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;SRAM re-initialization or loss of SRAM validity&lt;/STRONG&gt;?&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Could you also please confirm whether this behavior is expected by design on&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K394&lt;/STRONG&gt;&lt;SPAN&gt;?&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;This distinction is important for our software architecture, because we currently rely on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM retention across functional resets&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for communication between Boot Manager, Bootloader, and Application.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;</description>
    <pubDate>Thu, 07 May 2026 03:58:33 GMT</pubDate>
    <dc:creator>SBalaji</dc:creator>
    <dc:date>2026-05-07T03:58:33Z</dc:date>
    <item>
      <title>S32K394: Clarification on STCU2 self-test and system RAM retention across functional reset</title>
      <link>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2360844#M58376</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;With reference to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;“&lt;A href="https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2044460" target="_blank"&gt;S32K344 STCU BIST quest - NXP Community&lt;/A&gt;”&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;on the NXP Community, I would like to request clarification regarding the interaction between&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;STCU2 self-test&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;system RAM retention across functional reset&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K394&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;In&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Chapter 29.8, “System RAM retention across functional reset”&lt;/STRONG&gt;, the Reference Manual&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K396RM Rev. 4, 11/2024&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;states that:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;system RAM retains content during functional reset&lt;/LI&gt;&lt;LI&gt;retention is ensured through the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;crossbar halt handshake&lt;/STRONG&gt;&lt;/LI&gt;&lt;LI&gt;this applies to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;system RAMs only&lt;/STRONG&gt;&lt;/LI&gt;&lt;LI&gt;this does&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;not&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;apply to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;HSE_B&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;or&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;peripheral memories&lt;/STRONG&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Based on this description, my understanding is that&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;system SRAM contents should remain valid across a functional reset&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;However, in the context of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;STCU2 self-test&lt;/STRONG&gt;, it appears that SRAM contents may no longer be preserved, even though the resulting reset is treated as a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Therefore, I would appreciate confirmation of the following interpretation:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset itself&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;still preserves system RAM&lt;/LI&gt;&lt;LI&gt;but the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;STCU2 self-test operation&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;may already modify or overwrite or invalidate SRAM contents before that reset occurs&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Could you please confirm whether this interpretation is correct for&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K394&lt;/STRONG&gt;?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 06 May 2026 05:21:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2360844#M58376</guid>
      <dc:creator>SBalaji</dc:creator>
      <dc:date>2026-05-06T05:21:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K394: Clarification on STCU2 self-test and system RAM retention across functional reset</title>
      <link>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361212#M58392</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/260349"&gt;@SBalaji&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;1. Yes, the SRAM content is preserved across functional resets.&lt;/P&gt;
&lt;P&gt;2. Yes, this is the problem as the MBIST is executed over the entire SRAM, which overwrites its contents.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1778071509310.png" style="width: 1002px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/384496i24ABCDC78C77F19C/image-dimensions/1002x219?v=v2" width="1002" height="219" role="button" title="danielmartynek_0-1778071509310.png" alt="danielmartynek_0-1778071509310.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1778071601468.png" style="width: 706px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/384497iF2C2139039012E9C/image-dimensions/706x558?v=v2" width="706" height="558" role="button" title="danielmartynek_1-1778071601468.png" alt="danielmartynek_1-1778071601468.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The SPD/SAF BIST driver supports only two configurations, both of which execute MBIST across the entire SRAM.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_2-1778071742237.png" style="width: 521px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/384498iA12992BC95AFB17B/image-dimensions/521x344?v=v2" width="521" height="344" role="button" title="danielmartynek_2-1778071742237.png" alt="danielmartynek_2-1778071742237.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 06 May 2026 12:52:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361212#M58392</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-05-06T12:52:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32K394: Clarification on STCU2 self-test and system RAM retention across functional reset</title>
      <link>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361506#M58405</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Many thanks for your response.&lt;/P&gt;&lt;P&gt;Our project uses the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;region to exchange information between three different software images:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Boot Manager&lt;/STRONG&gt;,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Bootloader&lt;/STRONG&gt;, and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Application&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Only after a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Power-on Reset / Destructive Reset,&lt;/STRONG&gt;&amp;nbsp;the Boot Manager initialize this Standby SRAM region.&lt;/P&gt;&lt;P&gt;After a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;, this memory region is intentionally left untouched so that it can retain useful information for the other software images.&lt;/P&gt;&lt;P&gt;The current issue for us is that after&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;BIST self-test&lt;/STRONG&gt;, the SRAM contents appear to be invalidated, even though the resulting reset is a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;As a result, when the Boot Manager later reads a value from&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM&lt;/STRONG&gt;, it triggers an exception.&lt;/P&gt;&lt;P&gt;Our assumption, based on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Section 29.2.2 "Chip reset types"&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K396RM Rev. 4, 11/2024&lt;/STRONG&gt;, is that&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;loss of SRAM contents should be associated with destructive reset&lt;/STRONG&gt;, not functional reset.&lt;/P&gt;&lt;P&gt;Therefore, we would like to understand the following:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there a specific reason why&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;BIST self-test&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;results in a&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;functional reset&lt;/STRONG&gt;, even though it appears to cause&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;SRAM re-initialization or loss of SRAM validity&lt;/STRONG&gt;?&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Could you also please confirm whether this behavior is expected by design on&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;S32K394&lt;/STRONG&gt;&lt;SPAN&gt;?&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;This distinction is important for our software architecture, because we currently rely on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;Standby SRAM retention across functional resets&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for communication between Boot Manager, Bootloader, and Application.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;</description>
      <pubDate>Thu, 07 May 2026 03:58:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361506#M58405</guid>
      <dc:creator>SBalaji</dc:creator>
      <dc:date>2026-05-07T03:58:33Z</dc:date>
    </item>
    <item>
      <title>Re: S32K394: Clarification on STCU2 self-test and system RAM retention across functional reset</title>
      <link>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361614#M58412</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/260349"&gt;@SBalaji&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The SRAM content is retained across all functional resets, including the ST_DONE STCU2 reset.&lt;BR /&gt;However, the BIST driver triggers an MBIST operation on the entire SRAM before the functional reset. Since the MBIST is destructive, it overwrites the SRAM contents.&lt;BR /&gt;As a result, although the reset itself does not clear the SRAM, the data are effectively lost due to the preceding MBIST execution. Therefore, reinitialization of the SRAM is required.&lt;BR /&gt;This behavior is expected.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Thu, 07 May 2026 07:13:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K394-Clarification-on-STCU2-self-test-and-system-RAM/m-p/2361614#M58412</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-05-07T07:13:42Z</dc:date>
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