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    <title>S32KのトピックRe: Clarification on CAN0 pin combinations in S32K311</title>
    <link>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354167#M58098</link>
    <description>&lt;P&gt;&lt;A href="https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/S32k3-Can/td-p/2048950" target="_blank"&gt;S32k3:Can - NXP Community&lt;/A&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 21 Apr 2026 09:27:40 GMT</pubDate>
    <dc:creator>db16122</dc:creator>
    <dc:date>2026-04-21T09:27:40Z</dc:date>
    <item>
      <title>Clarification on CAN0 pin combinations in S32K311</title>
      <link>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354064#M58091</link>
      <description>&lt;P&gt;Hi NXP Team,&lt;/P&gt;&lt;P&gt;I am working on the NXP S32K311 and need clarification regarding CAN0 pin multiplexing. From the reference manual and pin configuration tools, I understand that CAN0 can be routed through specific pin pairs such as:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;PTB0 (CAN0_RX) and PTB1 (CAN0_TX)&lt;/LI&gt;&lt;LI&gt;PTC2 (CAN0_RX) and PTC3 (CAN0_TX)&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;In our current hardware design, CAN0 is connected using:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;PTB0 as CAN0_RX&lt;/LI&gt;&lt;LI&gt;PTC3 as CAN0_TX&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Observation:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;CAN communication works intermittently&lt;/LI&gt;&lt;LI&gt;Errors (CRC/ACK/bit errors) are observed under certain conditions&lt;/LI&gt;&lt;LI&gt;Behaviour varies across boards&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Questions:&lt;/STRONG&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is mixing CAN0 RX and TX pins across different groups (e.g., PTB0 + PTC3) a supported configuration on S32K311?&lt;/LI&gt;&lt;LI&gt;If not supported, could you confirm that this may lead to intermittent or undefined CAN behaviour?&lt;/LI&gt;&lt;LI&gt;Are there any internal routing or SIUL2 limitations that require RX/TX to be selected strictly from the same pin pair?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;We require above information from you to validate this as the root cause of the observed issue.&lt;/P&gt;&lt;P&gt;Thanks in advance for your support &lt;LI-PRODUCT title="S32DS-ARM" id="S32DS-ARM"&gt;&lt;/LI-PRODUCT&gt;&amp;nbsp;&lt;LI-PRODUCT title="S32K31XEVB-Q100" id="S32K31XEVB-Q100"&gt;&lt;/LI-PRODUCT&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 21 Apr 2026 06:41:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354064#M58091</guid>
      <dc:creator>yusupkhan241</dc:creator>
      <dc:date>2026-04-21T06:41:08Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on CAN0 pin combinations in S32K311</title>
      <link>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354167#M58098</link>
      <description>&lt;P&gt;&lt;A href="https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/S32k3-Can/td-p/2048950" target="_blank"&gt;S32k3:Can - NXP Community&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 21 Apr 2026 09:27:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354167#M58098</guid>
      <dc:creator>db16122</dc:creator>
      <dc:date>2026-04-21T09:27:40Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on CAN0 pin combinations in S32K311</title>
      <link>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354224#M58103</link>
      <description>&lt;P&gt;We observe that CAN0 is currently configured using PTB0 (RX) and PTC3 (TX), i.e., signals are selected from different pin groups.&lt;/P&gt;&lt;P&gt;Based on observed intermittent communication errors (CRC, ACK, bit errors), we suspect that mixing RX/TX across different pin groups may not be a validated or recommended configuration on NXP S32K311.&lt;/P&gt;&lt;P&gt;Could you please confirm whether CAN RX and TX must be selected strictly from the same predefined pin pair (e.g., PTB0/PTB1 or PTC2/PTC3) due to SIUL2/internal routing constraints?&lt;/P&gt;</description>
      <pubDate>Tue, 21 Apr 2026 11:19:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2354224#M58103</guid>
      <dc:creator>yusupkhan241</dc:creator>
      <dc:date>2026-04-21T11:19:43Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on CAN0 pin combinations in S32K311</title>
      <link>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2355233#M58145</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;1. Is mixing CAN0 RX and TX pins across different groups (e.g., PTB0 + PTC3) a supported configuration on S32K311?&lt;BR /&gt;A: yes, this is possible. Those pins are different pad types, but it should not be an issue, considering pin rates etc&lt;BR /&gt;&lt;BR /&gt;2. If not supported, could you confirm that this may lead to intermittent or undefined CAN behaviour?&lt;BR /&gt;&lt;BR /&gt;3. Are there any internal routing or SIUL2 limitations that require RX/TX to be selected strictly from the same pin pair?&lt;BR /&gt;A: you should properly set the MSCR and IMCR registers to select desired functionality on used pin&lt;BR /&gt;TX on PTC3: set MSCR67 OBE=1, SSS=3&lt;BR /&gt;RX on PTB0: set MSCR32 IBE=1 and IMCR0.SSS=3&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Thu, 23 Apr 2026 12:49:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Clarification-on-CAN0-pin-combinations-in-S32K311/m-p/2355233#M58145</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2026-04-23T12:49:52Z</dc:date>
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