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  <channel>
    <title>topic Re: Free RTOS heap memory changed from SRAM0 to DTCM in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353647#M58076</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238723"&gt;@Omkar9903&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Could you please clarify what you mean by “FreeRTOS is not functioning correctly”?&lt;BR /&gt;For example, does the scheduler fail to start, do tasks not run, or are you encountering a HardFault?&lt;BR /&gt;Also, can you ensure that the .my_heap section is aligned in the same way as the default .heap section.&lt;/P&gt;
&lt;P&gt;Finally, please provide the following details so the issue can be analyzed accurately:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;MCU variant&lt;/LI&gt;
&lt;LI&gt;RTD version&lt;/LI&gt;
&lt;LI&gt;FreeRTOS RTD extension version&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 20 Apr 2026 10:37:38 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2026-04-20T10:37:38Z</dc:date>
    <item>
      <title>Free RTOS heap memory changed from SRAM0 to DTCM</title>
      <link>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353011#M58039</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using &lt;STRONG&gt;FreeRTOS with heap_1.c&lt;/STRONG&gt;, and the configuration&lt;BR /&gt;configAPPLICATION_ALLOCATED_HEAP = 1 is enabled.&lt;/P&gt;&lt;P&gt;I have allocated the FreeRTOS heap in &lt;STRONG&gt;DTCM RAM&lt;/STRONG&gt; from main.c as shown below:&lt;/P&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;__attribute__((section(".my_heap")));&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;In the linker script, I have mapped the heap section to DTCM memory as follows:&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;/* Heap section */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;/* Data tightly coupled memory (D-TCM) */&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;dtcm (rw) : &lt;SPAN&gt;ORIGIN&lt;/SPAN&gt; = 0x20000000, &lt;SPAN&gt;LENGTH&lt;/SPAN&gt; = 0x1F000 &lt;SPAN&gt;/* 124KB Data RAM */&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;stack_dtcm (rw) : &lt;SPAN&gt;ORIGIN&lt;/SPAN&gt; = 0x2001F000, &lt;SPAN&gt;LENGTH&lt;/SPAN&gt; = 0x1000 &lt;SPAN&gt;/* 4KB */&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;.bss_tcm_data (NOLOAD) :&lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;. = &lt;SPAN&gt;ALIGN&lt;/SPAN&gt;(4);&lt;/P&gt;&lt;P&gt;__dtcm_bss_start__ = .;&lt;/P&gt;&lt;P&gt;*(.dtcm_bss*)&lt;/P&gt;&lt;P&gt;. = &lt;SPAN&gt;ALIGN&lt;/SPAN&gt;(4);&lt;/P&gt;&lt;P&gt;__dtcm_bss_end__ = .;&lt;/P&gt;&lt;P&gt;*(.my_heap)&lt;/P&gt;&lt;P&gt;} &amp;gt; dtcm&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;.heap (NOLOAD) :&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; . = ALIGN(4);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _end = .;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; end = .;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _heap_start = .;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; . += HEAP_SIZE;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; _heap_end = .;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;} &amp;gt; dtcm&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;.my_heap (NOLOAD) :&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; *(.my_heap)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;} &amp;gt; dtcm&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;&lt;P&gt;The .map file confirms that the heap memory has been placed in DTCM.&lt;BR /&gt;However, after this change, &lt;STRONG&gt;FreeRTOS is not functioning correctly&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Could you please help review this setup and advise on what might be missing or incorrect?&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 17 Apr 2026 13:48:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353011#M58039</guid>
      <dc:creator>Omkar9903</dc:creator>
      <dc:date>2026-04-17T13:48:01Z</dc:date>
    </item>
    <item>
      <title>Re: Free RTOS heap memory changed from SRAM0 to DTCM</title>
      <link>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353647#M58076</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238723"&gt;@Omkar9903&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Could you please clarify what you mean by “FreeRTOS is not functioning correctly”?&lt;BR /&gt;For example, does the scheduler fail to start, do tasks not run, or are you encountering a HardFault?&lt;BR /&gt;Also, can you ensure that the .my_heap section is aligned in the same way as the default .heap section.&lt;/P&gt;
&lt;P&gt;Finally, please provide the following details so the issue can be analyzed accurately:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;MCU variant&lt;/LI&gt;
&lt;LI&gt;RTD version&lt;/LI&gt;
&lt;LI&gt;FreeRTOS RTD extension version&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Apr 2026 10:37:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353647#M58076</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-04-20T10:37:38Z</dc:date>
    </item>
    <item>
      <title>Re: Free RTOS heap memory changed from SRAM0 to DTCM</title>
      <link>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353696#M58078</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I am using s32k341 microcontroller with RTD version 5.0.0 and RTOS version&amp;nbsp;&lt;SPAN&gt;FreeRTOS Kernel V10.5.0.&lt;BR /&gt;&lt;BR /&gt;The issue is observed that we are getting hard fault from clock init function i.e "Clock_Ip_SetWaitStates"&lt;/SPAN&gt;&lt;SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;P&gt;I have declared the heap array in main.c as follows:&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;SPAN class=""&gt;UNSIGNED8 ucHeap[8712] __attribute__((section(".dtcm_bss")));&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;I have verified in the &lt;STRONG&gt;MAP file&lt;/STRONG&gt; that ucHeap is correctly allocated in &lt;STRONG&gt;DTCM memory&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;I am attaching my &lt;STRONG&gt;linker file&lt;/STRONG&gt; for review.&lt;BR /&gt;Please let me know if anything is missing or incorrectly configured.&lt;/P&gt;&lt;P&gt;snapshot of map file :&lt;/P&gt;&lt;P&gt;note main.c is renamed as sid.c&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Omkar9903_0-1776686466120.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/382969i92772C887B750BA6/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Omkar9903_0-1776686466120.png" alt="Omkar9903_0-1776686466120.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 20 Apr 2026 12:14:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2353696#M58078</guid>
      <dc:creator>Omkar9903</dc:creator>
      <dc:date>2026-04-20T12:14:47Z</dc:date>
    </item>
    <item>
      <title>Re: Free RTOS heap memory changed from SRAM0 to DTCM</title>
      <link>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2354544#M58111</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238723"&gt;@Omkar9903&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;How is&amp;nbsp;&lt;SPAN&gt;portBYTE_ALIGNMENT&lt;/SPAN&gt;&amp;nbsp;defined in portmacro.h&lt;/P&gt;
&lt;P&gt;&lt;A href="https://forums.freertos.org/t/memory-alignment-in-heap-1-c-file/13355" target="_blank"&gt;https://forums.freertos.org/t/memory-alignment-in-heap-1-c-file/13355&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;The heap should be aligned to that number of bytes.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regarding the fault exception, try to find more information about it:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 22 Apr 2026 06:58:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Free-RTOS-heap-memory-changed-from-SRAM0-to-DTCM/m-p/2354544#M58111</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-04-22T06:58:07Z</dc:date>
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