S32KのトピックRe: S32K324 : Memory Layout

S32K324 : Memory Layout

RIJILKP — Mon, 06 Apr 2026 16:08:55 GMT

I am looking for the Memory layout of the S32K324 MCU, could not find it in Data Sheet.

Do you have any document which list the starting address and size of each type of memory sections available in MCU like(Pflash, RAM, etc)

Re: S32K324 : Memory Layout

Senlent — Tue, 07 Apr 2026 07:17:32 GMT

Hi@RIJILKP

A.S32K3‘s memory info can be found in Reference Manual's attachments.

2.AN13388: S32K3 Memories Guide;

https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/S32K/37044/2/AN13388.pdf

Re: S32K324 : Memory Layout

RIJILKP — Tue, 07 Apr 2026 13:41:17 GMT

I could not find the attachment in the above document, it is empty. Is it possible to upload the file here?

Re: S32K324 : Memory Layout

Senlent — Wed, 08 Apr 2026 01:36:05 GMT

Hi@RIJILKP

I attach it for your reference.

Re: S32K324 : Memory Layout

RIJILKP — Mon, 13 Apr 2026 18:48:46 GMT

Thanks for the document.

I have few questions based on that.

1. Why is the below sections start and stop at same address?

0x00000000	0x0000FFFF	64	ITCM_0	non-cacheable
0x00000000	0x0000FFFF	64	ITCM_1	non-cacheable
0x00000000	0x0000FFFF	64	ITCM_2	non-cacheable
0x00000000	0x0000FFFF	64	ITCM_3	non-cacheable

2. Is there any functional difference between Program flash (Block 0) and Program flash (Block 1)?

3. Is there any functional difference between PFC1 and PFC0?

I could not find these details in the data sheet and memory guide, if you have any other document for the memory details that will help.

Re: S32K324 : Memory Layout

RIJILKP — Mon, 13 Apr 2026 20:41:00 GMT

Could you also share some documents for OTA implementation on S32k324.

If you have any app notes for that it will help, Also I am looking for how the A/B swap works with your HSE/Secure boot.

Re: S32K324 : Memory Layout

RIJILKP — Mon, 13 Apr 2026 22:17:45 GMT

do you have a sample linker file for OTA support with A/B swap, just want to know how my memory organization should be done.

Re: S32K324 : Memory Layout

Senlent — Tue, 14 Apr 2026 02:40:48 GMT

Hi@RIJILKP

In the Cortex-M7, the ITCM and DTCM are dedicated ports (I-TCM Port / D-TCM Port) directly connected to the core, and are not part of the system bus address.

Therefore, for each core:

The ITCM address 0x0000_0000 refers to that core's private ITCM.

This ITCM is completely invisible to other cores.

In a multi-core system, each core has its own ITCM, but the address remains fixed.

The different blocks are largely the same, except for their addresses.

PCFx should be present in the S32K389 series MCUs; the S32K324 does not have this module.

Regarding the HSE issue, please create a case:https://support.nxp.com/s/?language=en_US