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    <title>topic Re: S32K324 UTest NVM OTP location writing fails in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2342185#M57608</link>
    <description>&lt;P&gt;I checked writing to DFLASH works. I tried on address 0x1001f770 for S2K324. It works fine. Just address is different code is same. Same code does not work for writing to UTEST DCF memory areas address range from&amp;nbsp;&lt;SPAN&gt;0x1B000770U.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 30 Mar 2026 12:45:18 GMT</pubDate>
    <dc:creator>anilsp31PA</dc:creator>
    <dc:date>2026-03-30T12:45:18Z</dc:date>
    <item>
      <title>S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2340516#M57557</link>
      <description>&lt;P&gt;We want to write to S32K324 UTEST NVM OTP locations from 0x1B000770 onwards. But the Write API is failing with error code&amp;nbsp;&lt;/P&gt;&lt;P&gt;C40_IP_STATUS_ERROR_PROGRAM_VERIFY. We observed memory was not written properly. But C40_Ip_MainInterfaceWrite() API was successful.&lt;BR /&gt;We ran the C40_Ip_MainInterfaceWrite() and C40_Ip_MainInterfaceWriteStatus() functions from RAM.&lt;BR /&gt;Anything needs to be checked for failure?&lt;/P&gt;</description>
      <pubDate>Thu, 26 Mar 2026 17:34:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2340516#M57557</guid>
      <dc:creator>anilsp31PA</dc:creator>
      <dc:date>2026-03-26T17:34:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2340905#M57579</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229232"&gt;@anilsp31PA&lt;/a&gt;,&lt;/P&gt;
&lt;DIV style="font-family: 'Segoe UI'; font-size: 14px; font-style: normal; font-weight: 400; line-height: 20px;"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;Do you verify that the flash phrase you intend to program is fully erased (all 0xFF) before performing the write operation?&lt;/P&gt;
&lt;P&gt;You can refer to this example:&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-decouple-RTD400-Ip-C40-DS35/ta-p/1866329" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-decouple-RTD400-Ip-C40-DS35/ta-p/1866329&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;It may also help to test the write procedure on standard D-Flash first to confirm that the write behaves as expected.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;BR, Daniel&lt;/P&gt;</description>
      <pubDate>Fri, 27 Mar 2026 09:03:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2340905#M57579</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-03-27T09:03:44Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2341297#M57582</link>
      <description>&lt;P&gt;Yes, We are checking it locations are 0xFF before writing.&lt;/P&gt;&lt;P&gt;After running it from RAM we go it working once the first time for 8 bytes. But it returned error. Not sure which API failed. I was not debugging it.&lt;/P&gt;&lt;P&gt;Also, it never written again in next set of 8 locations. It returns error from&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;C40_Ip_Compare().&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 27 Mar 2026 14:36:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2341297#M57582</guid>
      <dc:creator>anilsp31PA</dc:creator>
      <dc:date>2026-03-27T14:36:58Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2342141#M57600</link>
      <description>&lt;P&gt;I have stopped C40_IP_PROGRAM_VERIFICATION_ENABLED. Now it is writing successfully.&lt;BR /&gt;But giving HardFault in C40_Ip_MainInterfaceHVJobStatus().&lt;/P&gt;</description>
      <pubDate>Mon, 30 Mar 2026 10:48:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2342141#M57600</guid>
      <dc:creator>anilsp31PA</dc:creator>
      <dc:date>2026-03-30T10:48:52Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2342185#M57608</link>
      <description>&lt;P&gt;I checked writing to DFLASH works. I tried on address 0x1001f770 for S2K324. It works fine. Just address is different code is same. Same code does not work for writing to UTEST DCF memory areas address range from&amp;nbsp;&lt;SPAN&gt;0x1B000770U.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 30 Mar 2026 12:45:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2342185#M57608</guid>
      <dc:creator>anilsp31PA</dc:creator>
      <dc:date>2026-03-30T12:45:18Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2344763#M57694</link>
      <description>&lt;P&gt;This worked after putting respective functions to run from RAM. Only thing is now I am trying to find better way to use macro&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;MEM_43_INFLS_START_SEC_RAMCODE to put whole C40 driver to run from RAM. But that is not happening. May need some more understanding on this.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 02 Apr 2026 18:18:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2344763#M57694</guid>
      <dc:creator>anilsp31PA</dc:creator>
      <dc:date>2026-04-02T18:18:14Z</dc:date>
    </item>
    <item>
      <title>Re: S32K324 UTest NVM OTP location writing fails</title>
      <link>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2346035#M57747</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229232"&gt;@anilsp31PA&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The C40_Ip is placed in SRAM in this example:&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-C40-Ip-SRAM-RTD-500-DS35/ta-p/2074245" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-C40-Ip-SRAM-RTD-500-DS35/ta-p/2074245&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;However, I would recommend using the MCAL INFLS driver instead. When the option “Mem Load Access Code On Job Start” is enabled, the necessary code is automatically loaded into SRAM, eliminating the need for manual placement.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&lt;/P&gt;
&lt;DIV id="tinyMceEditordanielmartynek_0" class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 07 Apr 2026 06:57:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K324-UTest-NVM-OTP-location-writing-fails/m-p/2346035#M57747</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2026-04-07T06:57:41Z</dc:date>
    </item>
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