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  <channel>
    <title>topic Re: GD3162 Daisy Chain in S32K</title>
    <link>https://community.nxp.com/t5/S32K/GD3162-Daisy-Chain/m-p/2338225#M57487</link>
    <description>&lt;P&gt;Dear Q&lt;SPAN&gt;ian,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;all six GD3162 devices share the same MOSI / MISO / SCLK / CSB. The devices are connected in series, forming one long shift register.&amp;nbsp;&lt;SPAN&gt;Each GD3162 requires a &lt;/SPAN&gt;24‑bit frame. Please refer to the section 12. in the GD3162 full datasheet for the SPI interface description.&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot_1.png" style="width: 457px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380166i1F148317145E39AC/image-dimensions/457x83?v=v2" width="457" height="83" role="button" title="Screenshot_1.png" alt="Screenshot_1.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;
&lt;DIV&gt;Please download the full GD3162 datasheet from the &lt;A href="https://www.nxp.com/products/GD3162?ticket=ST-8775-oubUc-NwaKx7a5HvKdKjIcWFsXo-nxp#myDocument" target="_self"&gt;GD3162 product page&lt;/A&gt;, under the Secure section.&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot_2.png" style="width: 430px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380168i7CEBBA6A743E8E2C/image-dimensions/430x233?v=v2" width="430" height="233" role="button" title="Screenshot_2.png" alt="Screenshot_2.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;
&lt;DIV&gt;In the Figure 43. is shown SPI timing, from which required SPI mode can be deduced.&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="JozefKozon_0-1774339042724.png" style="width: 337px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380169iCDBF0C6E12C6B111/image-dimensions/337x194?v=v2" width="337" height="194" role="button" title="JozefKozon_0-1774339042724.png" alt="JozefKozon_0-1774339042724.png" /&gt;&lt;/span&gt;
&lt;DIV id="tinyMceEditorJozefKozon_0" class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;TABLE class="wikitable"&gt;
&lt;TBODY&gt;
&lt;TR&gt;
&lt;TH width="90.8681px" height="75px"&gt;SPI mode&lt;/TH&gt;
&lt;TH width="115.66px" height="75px"&gt;Clock polarity&lt;BR /&gt;(CPOL)&lt;/TH&gt;
&lt;TH width="104.618px" height="75px"&gt;Clock phase&lt;BR /&gt;(CPHA)&lt;/TH&gt;
&lt;TH width="287.674px" height="75px"&gt;Data is shifted out on&lt;/TH&gt;
&lt;TH width="148.75px" height="75px"&gt;Data is sampled on&lt;/TH&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;falling SCLK, and when&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;SS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;activates&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;2&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;rising SCLK, and when&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;SS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;activates&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;3&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;
&lt;P&gt;Figure 47. shows Daisy chain data transmission.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In the Table 34. are listed SPI registers.&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;
&lt;P&gt;Do I need to configure registers first?&lt;/P&gt;
&lt;P&gt;&lt;FONT color="#0000FF"&gt;[A] Yes. All GD3162 devices must receive their configuration via SPI before entering normal PWM operation.&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT color="#0000FF"&gt;If some devices need different settings, write to all first, then overwrite the ones that differ. Add 100us delay after each register write.&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;
&lt;DIV&gt;With Best Regards,&lt;/DIV&gt;
&lt;DIV&gt;Jozef&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
    <pubDate>Tue, 24 Mar 2026 08:03:57 GMT</pubDate>
    <dc:creator>JozefKozon</dc:creator>
    <dc:date>2026-03-24T08:03:57Z</dc:date>
    <item>
      <title>GD3162 Daisy Chain</title>
      <link>https://community.nxp.com/t5/S32K/GD3162-Daisy-Chain/m-p/2338128#M57479</link>
      <description>&lt;P&gt;Using the serial mode with the MCU to access 6 GD3162 devices, could you please explain how to configure the EB? Also, do I need to first set the working parameters using the registers, and then send and receive data? How should I send and receive data? I have read the official GD3162 sample code, but I don't understand how to use the daisy chain method to enable the MCU to communicate with the 6 driving peripherals.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Mar 2026 05:49:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/GD3162-Daisy-Chain/m-p/2338128#M57479</guid>
      <dc:creator>xingyun</dc:creator>
      <dc:date>2026-03-24T05:49:09Z</dc:date>
    </item>
    <item>
      <title>Re: GD3162 Daisy Chain</title>
      <link>https://community.nxp.com/t5/S32K/GD3162-Daisy-Chain/m-p/2338225#M57487</link>
      <description>&lt;P&gt;Dear Q&lt;SPAN&gt;ian,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;all six GD3162 devices share the same MOSI / MISO / SCLK / CSB. The devices are connected in series, forming one long shift register.&amp;nbsp;&lt;SPAN&gt;Each GD3162 requires a &lt;/SPAN&gt;24‑bit frame. Please refer to the section 12. in the GD3162 full datasheet for the SPI interface description.&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot_1.png" style="width: 457px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380166i1F148317145E39AC/image-dimensions/457x83?v=v2" width="457" height="83" role="button" title="Screenshot_1.png" alt="Screenshot_1.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;
&lt;DIV&gt;Please download the full GD3162 datasheet from the &lt;A href="https://www.nxp.com/products/GD3162?ticket=ST-8775-oubUc-NwaKx7a5HvKdKjIcWFsXo-nxp#myDocument" target="_self"&gt;GD3162 product page&lt;/A&gt;, under the Secure section.&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot_2.png" style="width: 430px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380168i7CEBBA6A743E8E2C/image-dimensions/430x233?v=v2" width="430" height="233" role="button" title="Screenshot_2.png" alt="Screenshot_2.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;
&lt;DIV&gt;In the Figure 43. is shown SPI timing, from which required SPI mode can be deduced.&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="JozefKozon_0-1774339042724.png" style="width: 337px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/380169iCDBF0C6E12C6B111/image-dimensions/337x194?v=v2" width="337" height="194" role="button" title="JozefKozon_0-1774339042724.png" alt="JozefKozon_0-1774339042724.png" /&gt;&lt;/span&gt;
&lt;DIV id="tinyMceEditorJozefKozon_0" class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;TABLE class="wikitable"&gt;
&lt;TBODY&gt;
&lt;TR&gt;
&lt;TH width="90.8681px" height="75px"&gt;SPI mode&lt;/TH&gt;
&lt;TH width="115.66px" height="75px"&gt;Clock polarity&lt;BR /&gt;(CPOL)&lt;/TH&gt;
&lt;TH width="104.618px" height="75px"&gt;Clock phase&lt;BR /&gt;(CPHA)&lt;/TH&gt;
&lt;TH width="287.674px" height="75px"&gt;Data is shifted out on&lt;/TH&gt;
&lt;TH width="148.75px" height="75px"&gt;Data is sampled on&lt;/TH&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;falling SCLK, and when&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;SS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;activates&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;2&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;0&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;rising SCLK, and when&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;SS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;activates&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD width="90.8681px" height="25px"&gt;3&lt;/TD&gt;
&lt;TD width="115.66px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="104.618px" height="25px"&gt;1&lt;/TD&gt;
&lt;TD width="287.674px" height="25px"&gt;falling SCLK&lt;/TD&gt;
&lt;TD width="148.75px" height="25px"&gt;rising SCLK&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;
&lt;P&gt;Figure 47. shows Daisy chain data transmission.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In the Table 34. are listed SPI registers.&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;
&lt;P&gt;Do I need to configure registers first?&lt;/P&gt;
&lt;P&gt;&lt;FONT color="#0000FF"&gt;[A] Yes. All GD3162 devices must receive their configuration via SPI before entering normal PWM operation.&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT color="#0000FF"&gt;If some devices need different settings, write to all first, then overwrite the ones that differ. Add 100us delay after each register write.&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;
&lt;DIV&gt;With Best Regards,&lt;/DIV&gt;
&lt;DIV&gt;Jozef&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Tue, 24 Mar 2026 08:03:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/GD3162-Daisy-Chain/m-p/2338225#M57487</guid>
      <dc:creator>JozefKozon</dc:creator>
      <dc:date>2026-03-24T08:03:57Z</dc:date>
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