topic Re: Unable to trigger second clock gate update in S32K

Unable to trigger second clock gate update

kscz — Wed, 25 Feb 2026 04:51:41 GMT

I write to prtn1_cofb1_clken[req56] in order to enable power to the PLL. As per the manual, I write prtn1_pupd[trigger] and then 0x5AF0 into ctl_key immediately followed by 0xA50F ctl_key

I then wait for prtn1_pupd[trigger] to clear automatically.

This all works exactly as expected!

Later in the code, I have almost exactly the same set of steps - I write to prtn1_cofb2_clken[req74] in order to enable power to the lpuart0. As per the manual, I write prtn1_pupd[trigger] and then 0x5AF0 into ctl_key immediately followed by 0xA50F ctl_key

I then wait for prtn1_pupd[trigger] to clear automatically, but it never clears.

If I stack both clock enables before the first call to prtn1_pupd[trigger], then it appears both clocks get enabled, but I can't find where in the manual this behavior is documented. Am I just missing something?

I know Rust isn't officially supported, but if it helps, my code is here: https://github.com/kscz/mrcanhub/blob/bfb209c12baf23e9991345752ff6bd0a75b7d1c8/src/main.rs

Re: Unable to trigger second clock gate update

PetrS — Wed, 25 Feb 2026 13:09:35 GMT

Hi,

there should be no issue to request another partition update.
I see you switch core clock to PLL, then set AIPS_PLAT divider. The AIPS domain may temporarily exceed its maximum allowed frequency. Try to set the AIPS (and any other divisors) before switching the core clock to the PLL.

BR, Petr

Re: Unable to trigger second clock gate update

kscz — Wed, 25 Feb 2026 17:26:40 GMT

You were right on the money - I needed to put in all the divisors before switching. After changing that, everything worked!