topic Re: s32k396 resolver angle flips by pi after power cycling in S32K

s32k396 resolver angle flips by pi after power cycling

gzleng — Fri, 30 Jan 2026 04:25:08 GMT

hello nxp experts..

i'm using an EB Tresos based proj with sw resolver but some weird behavior occurs when the power is recycled: at certain angles, the next power up would produce an angle that is 180deg apart.

what i've checked: the sine/cos waveforms vs the excitation are the same before and after the power recycle. the amplitude of the differential sine/cosine signals are 1.5V amplitude. i have a x4 in the SDADC user gain setting.

what i cannot figure out: 1. how is the SWG as the excitation is synchronized with the SDADC ? i cannot seem to find the triggering mechanism. 2. how is the etpu synchronized with the SDADC? 3. i cannot find where in the eb tresos to set the SDADC to differential mode.. is it hidden or by default?

thanks for your attention

Re: s32k396 resolver angle flips by pi after power cycling

MilanBrejl — Tue, 03 Feb 2026 13:47:00 GMT

Hello @gzleng,

try to modify the Start Delay parameter. Set it to 1/4 of the excitation signal period, or 1/2 of the excitation signal period. This parameter sets the initial phase shift of the excitation signals. A proper settings enables to speed up the RDC start-up sequence by quick settle of excitation signal phase-shift adjustment. Wrong settings might cause what you see - that it sometimes settles to 0deg and sometimes to 180deg.

1. how is the SWG as the excitation is synchronized with the SDADC ? i cannot seem to find the triggering mechanism.

SDADC runs continuously. There is no way to trigger/adjust the sampling points. SDADC samples arrives to eTPU as buffers of 16+16 samples. We need that one period of a modulated signal fits perfectly into that buffer of 16+16 samples.
It is achieved the way, that the excitation signal is phase-shifted (delayed). The phase-shift is controlled by a slow PI controller (actually just I-controller). The error input to the controller is the zero-crossing error of sin/cos signals in the input buffers. When settled, the excitation signal delay is tuned, sin/cos input signals are aligned in the buffers, their samples number 0 and 16 are all zeros.

2. how is the etpu synchronized with the SDADC?

16 samples ready in SDADC output buffer -> DMA triggered -> DMA moves those samples to eTPU DATA RAM & links another DMA channel -> that DMA channel transfers a constant value from RAM to eTPU channel HSR -> a write to HSR evokes eTPU event -> eTPU processes the SDADC samples and updates resolver angle and speed.
This happens every 50usec @ 10kHz excitation. There are also faster configurations.
(simplified - DSPSS omitted, talking about just one SDADC signal instead of both sin & cos)
This way the processing of resolver angle is completely independent of the CPU. Not a single interrupt to the CPU.

3. i cannot find where in the eb tresos to set the SDADC to differential mode.. is it hidden or by default?

EB tresos: Adc->AdcHwUnit->AdcChannel

This example uses differential signal between AN0 and AN1 inputs as the input to ADC.

Re: s32k396 resolver angle flips by pi after power cycling

gzleng — Tue, 03 Feb 2026 17:21:17 GMT

thank you Milan, that explains well.

related to the synchronization: Sinewave gen is not in the EB or RTD, i see there is an option for SWG_PHA_ALIG_ACCEPT_WIN_xx register. does it play a role in the sampling process?

Re: s32k396 resolver angle flips by pi after power cycling

MilanBrejl — Wed, 04 Feb 2026 12:58:23 GMT

I checked my setting. The SWG acceptance window is +/-15%. It is maybe unnecessarily too wide. The excitation adaptation I-controller does not make such a change in one step.

/* Exit power down mode */
REG_BIT_CLEAR32(SGEN_Addr, SGEN_CTRL_PDS_MASK << SGEN_CTRL_PDS_SHIFT);

/* Wait for load output freq */
REG_BIT_SET32(SGEN_Addr, SGEN_WAVE_FREQ_WAIT << SGEN_CTRL_LDOS_SHIFT);

/* Amplitude CFG */
REG_BIT_SET32(SGEN_Addr, SGEN_IO_WAVE_AMPLITUDE << SGEN_CTRL_IOAMPL_SHIFT);

/* Phase aligenment acceptance window width */
REG_BIT_SET32(SGEN_Addr, SGEN_PHA_ALIG_ACCEPT_WIN_15 << SGEN_CTRL_WINDOW_SHIFT);

/* Error Interrupt Off */
REG_BIT_SET32(SGEN_Addr, SGEN_ERROR_INTERRUPT_OFF << SGEN_CTRL_SEMASK_SHIFT);

/* Trigger mode selection */
REG_BIT_SET32(SGEN_Addr, SGEN_IN_PHA_ALIG_TRIG_HW << SGEN_CTRL_TRIG_MODE_SHIFT);

/* Output wave frequency configuration */
REG_BIT_SET32(SGEN_Addr, SGEN_OUTPUT_FREQENCY << SGEN_CTRL_IOFREQ_SHIFT);

/* loaded output freq */
REG_BIT_SET32(SGEN_Addr, SGEN_WAVE_FREQ_LOAD << SGEN_CTRL_LDOS_SHIFT);