<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Debugging Issues When Using a Decoupled S32K344 as an S32K324 in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Debugging-Issues-When-Using-a-Decoupled-S32K344-as-an-S32K324/m-p/2295788#M56175</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Once you verify the core 1 is released from reset it should be accessible by debugger if no further protection was applied.&lt;/P&gt;
&lt;DIV style="font-family: 'Segoe UI'; font-size: 14px; font-style: normal; font-weight: 400; line-height: 20px;"&gt;
&lt;UL&gt;
&lt;LI&gt;
&lt;P&gt;Test A (Attach sequence):&lt;BR /&gt;Start a Core0 debug session first, run to the point where your code releases Core1, then attach a second debug session to Core1 (selecting &lt;EM&gt;Cortex‑M7_1&lt;/EM&gt; in your probe). If this works, the issue is likely bring‑up order or attach mode&lt;/P&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Test B (Minimal Core1 image):&lt;BR /&gt;Flash a trivial Core1 firmware (just loops); ensure Core0 sets the start address and releases Core1. If Core1 attaches now, the problem is in Core1 init or watchdog.&lt;/P&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Test C (Under‑reset attach to Core1): if apply to your debugger.&lt;BR /&gt;Try “connect under reset” for Core1, then immediately halt and inspect PC/VTOR to confirm the vector table address is valid. If VTOR points nowhere, fix the linker/ROM location&lt;/P&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;/DIV&gt;</description>
    <pubDate>Mon, 19 Jan 2026 08:25:19 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2026-01-19T08:25:19Z</dc:date>
    <item>
      <title>Debugging Issues When Using a Decoupled S32K344 as an S32K324</title>
      <link>https://community.nxp.com/t5/S32K/Debugging-Issues-When-Using-a-Decoupled-S32K344-as-an-S32K324/m-p/2295409#M56166</link>
      <description>&lt;P&gt;&lt;SPAN&gt;After the decoupling process, the S32K344 is equivalent to the S32K324. I created a dual-core project based on the S32K324, which contains two projects corresponding to Core 0 and Core 1. However, during debugging, even when using independent (per-core) debugging, I am only able to successfully debug Core 0, while Core 1 cannot be connected or debugged. Could you please advise on the possible reasons for this behavior? &lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 17 Jan 2026 12:44:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Debugging-Issues-When-Using-a-Decoupled-S32K344-as-an-S32K324/m-p/2295409#M56166</guid>
      <dc:creator>yanyanwang</dc:creator>
      <dc:date>2026-01-17T12:44:59Z</dc:date>
    </item>
    <item>
      <title>Re: Debugging Issues When Using a Decoupled S32K344 as an S32K324</title>
      <link>https://community.nxp.com/t5/S32K/Debugging-Issues-When-Using-a-Decoupled-S32K344-as-an-S32K324/m-p/2295788#M56175</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Once you verify the core 1 is released from reset it should be accessible by debugger if no further protection was applied.&lt;/P&gt;
&lt;DIV style="font-family: 'Segoe UI'; font-size: 14px; font-style: normal; font-weight: 400; line-height: 20px;"&gt;
&lt;UL&gt;
&lt;LI&gt;
&lt;P&gt;Test A (Attach sequence):&lt;BR /&gt;Start a Core0 debug session first, run to the point where your code releases Core1, then attach a second debug session to Core1 (selecting &lt;EM&gt;Cortex‑M7_1&lt;/EM&gt; in your probe). If this works, the issue is likely bring‑up order or attach mode&lt;/P&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Test B (Minimal Core1 image):&lt;BR /&gt;Flash a trivial Core1 firmware (just loops); ensure Core0 sets the start address and releases Core1. If Core1 attaches now, the problem is in Core1 init or watchdog.&lt;/P&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;Test C (Under‑reset attach to Core1): if apply to your debugger.&lt;BR /&gt;Try “connect under reset” for Core1, then immediately halt and inspect PC/VTOR to confirm the vector table address is valid. If VTOR points nowhere, fix the linker/ROM location&lt;/P&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;/DIV&gt;</description>
      <pubDate>Mon, 19 Jan 2026 08:25:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Debugging-Issues-When-Using-a-Decoupled-S32K344-as-an-S32K324/m-p/2295788#M56175</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2026-01-19T08:25:19Z</dc:date>
    </item>
  </channel>
</rss>

