S32KのトピックRe: rgmii

rgmii

胡峰 — Wed, 17 Sep 2025 01:32:58 GMT

HELLO NXP TEAM:

I am currently using the S32K388EVB_Q289 development board and debugging the RGMII communication of GMAC0. Some packets sent out by the TJA1120 can be captured via a network packet analyzer. However, pinging the development board from the debugging laptop yields no response. An oscilloscope shows that the data and clock on the RX pins of the TJA1120 chip are normal, but the S32K388 fails to enter the RX interrupt, while the TX interrupt is entered normally. I would like to ask how to troubleshoot this issue. No hardware modifications have been made, and the software routine is based on the RTD6.0 and TCPIP3.0 library routines, with GMAC1 modified to GMAC0.

Is there any available RGMII routine for the S32K388EVB development board?

Re: rgmii

PavelL — Wed, 17 Sep 2025 07:30:57 GMT

Hello @胡峰 ,

I'm experiencing the same issue. I've already reported the issue to the apps team.

I'll keep you updated on any progress.

Thank you for your patience.

Best regards,

Pavel

Re: rgmii

胡峰 — Mon, 22 Sep 2025 08:47:46 GMT

Hello, may I ask if there has been any progress?

Re: rgmii

PavelL — Mon, 22 Sep 2025 11:54:14 GMT

Hello @胡峰 ,

unfortunately, the apps are busy with other topics.

Anyway, I found that S32K388_gptp_ds example from S32K3xx gPTP Stack 1.0.0 works, i.e. GMAC0 is receiving and sending data. I didn't have time to look closer on that, maybe this week.

Best regards,

Pavel

Re: rgmii

PavelL — Thu, 02 Oct 2025 12:49:37 GMT

Hello @胡峰 ,

I found the root cause - there were missing IRQs for GMAC0. So, please add them to your Platform configuration:

You probably did those steps:

Change settings to GMAC0 for Pins and Clocks
Eth_43_GMAC shall have EthConfigSet/EthCtrlIdx = 0; EthGeneral/EthIndex = 0.
Also, the very first row in device_init shall be:

/* below is for GMAC0 RGMII */
 IP_DCM_GPR->DCMRWF3 |= DCM_GPR_DCMRWF3_MAC_RX_CLK_MUX_BYPASS(1U);
 IP_DCM_GPR->DCMRWF1 = (IP_DCM_GPR->DCMRWF1 & ~DCM_GPR_DCMRWF1_MAC_CONF_SEL_MASK) | DCM_GPR_DCMRWF1_MAC_CONF_SEL(1U) | DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN(1U);
/* below is for GMAC1 RGMII */
 IP_DCM_GPR->DCMRWF4 = (IP_DCM_GPR->DCMRWF4 & ~DCM_GPR_DCMRWF4_MAC2_CONF_SEL_MASK) | DCM_GPR_DCMRWF4_MAC2_CONF_SEL(1U) | DCM_GPR_DCMRWF4_MAC2_RX_CLK_MUX_BYPASS(1U);
 IP_DCM_GPR->DCMRWF2 |= DCM_GPR_DCMRWF2_MAC2_TX_RMII_CLK_LPBCK_EN(1U) | DCM_GPR_DCMRWF2_MAC2_LOOBPACK_CLK_SEL(1U);
 

Best regards,

Pavel

Re: rgmii

James_Zhang_SE — Tue, 06 Jan 2026 01:50:33 GMT

Hi Pavel,

I'm trying to run the lwip_baremetal_s32k388 example on S32K388EVB-Q289 eval board. I wanted to use GMAC0 with RGMII mode. I have done the steps you suggested, i.e. configured the pins and clock for GMAC0, changed the Idx's to 0, enabled the IRQs and added the lines to device_init. I have also modified the clocks to 125MHz for 1G speed.

However, when I run the project, the light for link blinked twice during upload process and then went off and I cannot ping from PC. Kindly suggest what else could have gone wrong.

Re: rgmii

PavelL — Wed, 07 Jan 2026 07:04:11 GMT

Hello @James_Zhang_SE ,

TX_CLK should be doubled - 250MHz. Please review your clocks accordingly to clock picture I shared on this thread:

https://community.nxp.com/t5/S32K/S32K388-RGMII-GMAC0-ethernet-cannot-ping/td-p/2271084

Best regards,

Pavel