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    <title>S32KのトピックRe: SAF sBoot CMU_FC Checks</title>
    <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2264908#M55536</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/258066"&gt;@ziwu&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;All the calculations can be found in the S32K3xx RM rev.11&lt;/P&gt;
&lt;P&gt;Section 56.5.2 Programming HFREF and LFREF.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
    <pubDate>Wed, 17 Dec 2025 11:15:42 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2025-12-17T11:15:42Z</dc:date>
    <item>
      <title>SAF sBoot CMU_FC Checks</title>
      <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2263889#M55479</link>
      <description>&lt;P&gt;I don't know how to set the parameters when I config the CMU_FC check in sBoot. I set some values as my understand and generate the code,&amp;nbsp;how are the generated LFREF and HFREF values derived based on the values I set?&amp;nbsp;Can you show the calculation process?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ziwu_0-1765883055953.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370213iC565527C4859678E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ziwu_0-1765883055953.png" alt="ziwu_0-1765883055953.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ziwu_1-1765883088726.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370214iB594C9A7625C350E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ziwu_1-1765883088726.png" alt="ziwu_1-1765883088726.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;in my opinion, the parameter I set above should compare with RCCR.REF_CNT/ HTCR.HFREF/LTCR.LFREF. if FXOSC=40M, how can I config CMU_FC0 check? when I should set RCCR.REF_CNT/ HTCR.HFREF/LTCR.LFREF? what's the values?&lt;/P&gt;</description>
      <pubDate>Tue, 16 Dec 2025 12:32:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2263889#M55479</guid>
      <dc:creator>ziwu</dc:creator>
      <dc:date>2025-12-16T12:32:27Z</dc:date>
    </item>
    <item>
      <title>Re: SAF sBoot CMU_FC Checks</title>
      <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2264908#M55536</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/258066"&gt;@ziwu&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;All the calculations can be found in the S32K3xx RM rev.11&lt;/P&gt;
&lt;P&gt;Section 56.5.2 Programming HFREF and LFREF.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Wed, 17 Dec 2025 11:15:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2264908#M55536</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-12-17T11:15:42Z</dc:date>
    </item>
    <item>
      <title>Re: SAF sBoot CMU_FC Checks</title>
      <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2266410#M55600</link>
      <description>&lt;P&gt;1. I check the RM Rev.11, I cannot get the result yet, what's the bus clock? is it system clock?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;2. I checked the EB tresos, the RCCR set as 0x50 when&amp;nbsp;“Mcu Register Value Optimization” enabled, all RCCR of CMU_FC0/3/4 are 0x50, why they are the same value? I can't get 0x50 by the following formula. How to get 0x50?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ziwu_0-1766105709787.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/370670i6DD3C1407A23C730/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ziwu_0-1766105709787.png" alt="ziwu_0-1766105709787.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 19 Dec 2025 00:55:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2266410#M55600</guid>
      <dc:creator>ziwu</dc:creator>
      <dc:date>2025-12-19T00:55:44Z</dc:date>
    </item>
    <item>
      <title>Re: SAF sBoot CMU_FC Checks</title>
      <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2269400#M55742</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/258066"&gt;@ziwu&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I'm sorry for the delay, I'm currently out of office, and I could not reply earlier.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The system clock should be set precisely to one of the clock options listed in the RM, e.g.&amp;nbsp;Table 157. Option A - High Performance mode (CORE_CLK @ 160 MHz).&lt;/P&gt;
&lt;P&gt;Then, Bus clock = Register interface clock = AIPS_SLOW_CLK&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1766930897683.png" style="width: 667px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/371270iF608CDC100C3D057/image-dimensions/667x95?v=v2" width="667" height="95" role="button" title="danielmartynek_1-1766930897683.png" alt="danielmartynek_1-1766930897683.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1766930828127.png" style="width: 638px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/371269i760F144FD10E2851/image-dimensions/638x144?v=v2" width="638" height="144" role="button" title="danielmartynek_0-1766930828127.png" alt="danielmartynek_0-1766930828127.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I currently cannot test the SAF sBoost driver.&lt;/P&gt;
&lt;P&gt;But the thresholds are also calculated and set by the MCAL MCU driver if the CMUs are enabled.&lt;/P&gt;
&lt;P&gt;Here is an example for S32DS IDE and RTD 6.0.0:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-MCAL-MCU-ClockMonitor-v1-0-S32DS36-RTD600/ta-p/2179976" target="_blank"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-MCAL-MCU-ClockMonitor-v1-0-S32DS36-RTD600/ta-p/2179976&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 28 Dec 2025 14:14:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2269400#M55742</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-12-28T14:14:26Z</dc:date>
    </item>
    <item>
      <title>Re: SAF sBoot CMU_FC Checks</title>
      <link>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2269418#M55745</link>
      <description>&lt;P&gt;Got it, thanks&lt;/P&gt;</description>
      <pubDate>Mon, 29 Dec 2025 01:10:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/SAF-sBoot-CMU-FC-Checks/m-p/2269418#M55745</guid>
      <dc:creator>ziwu</dc:creator>
      <dc:date>2025-12-29T01:10:01Z</dc:date>
    </item>
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